Low stress asymmetric dual side module
Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
1. A semiconductor package comprising:
a first substrate;
a second substrate;
a spacer coupled between the first substrate and the second substrate;
a lead frame between the first substrate and the second substrate; and
a molding compound at least partially encapsulating the lead frame;
wherein a perimeter of the first substrate only partially overlaps a perimeter of the second substrate and the perimeter of the second substrate only partially overlaps the perimeter of the first substrate when the first substrate and second substrate are coupled through the spacer.
2. The semiconductor package of claim 1 , wherein only a portion of the first substrate is coupled directly under the second substrate and only a portion of the second substrate is coupled directly over the first substrate.
3. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al 2 O 3 ) ceramic doped with zirconium dioxide (ZrO 2 ), a silicon nitride (Si 3 N 4 ) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof.
4. The semiconductor package of claim 1 , further comprising a heat sink coupled with one of the first substrate, the second substrate, or any combination thereof.
5. The semiconductor package of claim 1 , wherein the spacer is comprised of electrically conductive material and electrically couples the first substrate to the second substrate.
6. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.
7. A semiconductor package comprising:
a lead frame;
a first substrate mechanically and electrically coupled to a first side of the lead frame;
a second substrate mechanically and electrically coupled to a second side of the lead frame;
a spacer coupled to and between each of the first substrate and the second substrate; and
a molding compound at least partially encapsulating the first side and the second side of the lead frame;
wherein the first substrate and the second substrate are asymmetrically coupled through the spacer; and
wherein a perimeter of a first side of the first substrate extends beyond a perimeter of a first side of the second substrate and the perimeter of the first side of the second substrate extends beyond the perimeter of the first side of the first substrate.
8. The semiconductor package of claim 7 , wherein the first side of the first substrate faces the first side of the second substrate.
9. The semiconductor package of claim 7 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al 2 O 3 ) ceramic doped with zirconium dioxide (ZrO 2 ), a silicon nitride (Si 3 N 4 ) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof.
10. The semiconductor package of claim 7 , further comprising a heat sink coupled with one of a second side of the first substrate, a second side of the second substrate, or any combination thereof.
11. The semiconductor package of claim 7 , wherein the spacer is comprised of electrically conductive material and electrically couples the first substrate to the second substrate.
12. The semiconductor package of claim 7 , wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.
13. A semiconductor package comprising:
a first substrate coupled to a second substrate through a spacer;
a lead frame coupled between the first substrate and the second substrate; and
a molding compound at least partially encapsulating the lead frame;
wherein the first substrate and the second substrate are asymmetrically coupled through the lead frame.
14. The semiconductor package of claim 13 , wherein an outer edge of the first substrate extends beyond a perimeter of the second substrate and an outer edge of the second substrate extends beyond a perimeter of the first substrate.
15. The semiconductor package of claim 13 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al 2 O 3 ) ceramic doped with zirconium dioxide (ZrO 2 ), a silicon nitride (Si 3 N 4 ) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H-AlN) ceramic, or any combination thereof.
16. The semiconductor package of claim 13 , further comprising a heat sink coupled with one of the first substrate, the second substrate, or any combination thereof.
17. The semiconductor package of claim 13 , wherein the spacer is comprised of electrically conductive material and electrically couples the first substrate to the second substrate.
18. The semiconductor package of claim 13 , wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.
19. The semiconductor package of claim 13 , further comprising a plurality of clips coupled to the first substrate and the second substrate.
20. The semiconductor package of claim 13 , wherein a perimeter of a first side of the first substrate extends outside of a perimeter of a first side of the second substrate and the perimeter of the first side of the second substrate extends outside of the perimeter of the first side of the first substrate, wherein the first side of the first substrate faces the first side of the second substrate.