IP Library › Granted Patent US 12,556,140
Granted Patent B2
US 12,556,140 · App. 17/823,573 · Granted Feb 17, 2026

Broadband sliding-mode outphasing power amplifier with high efficiency

Inventors: Patrick Roblin (Columbus, OH); Dominic Mikrut (Columbus, OH)
Assignee: Ohio State Innovation Foundation
H03F1/0288H03F3/211H03F3/602H03F2200/451
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Quick Facts
Patent No.
US 12,556,140
App. No.
17/823,573
Granted
Feb 17, 2026
Kind
B2
Abstract

A dual-input microwave power amplifier (PA) with high-efficiency. The PA exploits the continuum of modes between the Doherty and Chireix PA mode of operation to achieve 40% fractional bandwidth while relying on the physical linear dispersion of the transmission lines of the lossless output combiner. A constant output is achieved at peak power over the entire bandwidth. The output backoff varies from 6 dB in the Doherty mode to 8 dB in the Chireix mode. The PA operates over a wider range of frequencies from 1 to 8 GHz. The dual-input PA operates in mixed-mode and thus requires variable input power drives and outphasing angle.

Claims (81)

1 . A dual transistor power amplifier (PA), comprising:

a main branch transmission line (TL 1 ) having a main transistor and having a characteristic impedance R opt ;

an auxiliary branch transmission line (TL 2 ) having an auxiliary transistor and having the characteristic impedance R opt ;

a common load (R L ) to which the main branch transmission line and the auxiliary branch transmission line are connected,

wherein the main branch transmission line (TL 1 ) and the auxiliary branch transmission line (TL 2 ) are matching networks established at a current-source reference plane (CSRP), and

wherein the dual transistor PA provides a sliding mode on a Chireix-Doherty continuum by mapping an electrical length of the main branch transmission TL 1 and an electrical length the auxiliary branch transmission TL 2 across a targeted frequency band of operation with an outphasing angle.

2 . The dual transistor power amplifier of claim 1 , wherein the electrical length is determined with the following relationship:

Θ

1

/

2

=

Θ

O

{

1

,

2

}

⁢

ω

ω

O

,

and

wherein

Θ

O

1

=

π

2

,

 Θ o 2 =π , ω=2πf, where f is a frequency of operation, wherein ω o =2πf H , where f H is a maximum frequency in a desired operating frequency range.

3 . The dual transistor power amplifier of claim 2 , wherein the dual transistor power amplifier operates in a Doherty mode of operation with 6 dB of output back-off (OBO) power at the maximum frequency when the outphasing angle between two inputs is equal to 90° which occurs when ω=ω o .

4 . The dual transistor power amplifier of claim 3 , wherein, as the frequency of operation deviates from ω o , the mode operation gradually changes from the Doherty mode of operation to a Chireix mode of operation with 8 dB of OBO power at a minimum frequency.

5 . The dual transistor power amplifier of claim 1 , wherein the dual transistor power amplifier provides 40% fractional bandwidth while relying on a physical linear dispersion of transmission lines of a lossless output combiner.

6 . The dual transistor power amplifier of claim 1 , wherein the dual transistor power amplifier provides a constant output at peak power over an entire bandwidth.

7 . The dual transistor power amplifier of claim 1 , wherein the common load maintains a predetermined impedance for the main transistor and the auxiliary transistor while an output power of the dual transistor power amplifier varies from a peak output power to a back-off output (OBO) power.

8 . The dual transistor power amplifier of claim 7 , wherein the common load provides a DC drain biasing for the dual transistor power amplifier.

9 . A method providing a sliding mode on a Chireix-Doherty continuum in a dual transistor power amplifier (PA) having a main branch transmission line (TL 1 ) having a main transistor and having a characteristic impedance R opt , an auxiliary branch transmission line (TL 2 ) having an auxiliary transistor and having the characteristic impedance R opt , and a common load (R L ) to which the mail branch transmission line and the auxiliary branch transmission line are connected, comprising:

establishing, at a current-source reference plane (CSRP), the main branch transmission line (TL 1 ) and the auxiliary branch transmission line (TL 2 ) as matching networks; and

mapping an electrical length of the main branch transmission TL 1 and an electrical length the auxiliary branch transmission TL 2 across a targeted frequency band of operation with an outphasing angle.

10 . The method of claim 9 , further comprising:

determining the electrical length of transmission lines according to:

Θ

1

/

2

=

Θ

O

{

1

,

2

}

⁢

ω

ω

O

,

and

wherein

Θ

O

1

=

π

2

,

 Θ O 2 =π , and ω=2πf, where f is a frequency of operation, ω o =2πf H , where f H is a maximum frequency in a desired operating frequency range.

11 . The method of claim 10 , further comprising operating the dual transistor power amplifier operates in a Doherty mode of operation with 6 dB of output back-off (OBO) power at a maximum frequency when the outphasing angle between two inputs is equal to 90° which occurs when ω=ω o .

12 . The method of claim 11 , further comprising:

varying a frequency of operation from ω o ; and

changing the mode operation from the Doherty mode of operation to a Chireix mode of operation with 8 dB of OBO power at the minimum frequency.

13 . The method of claim 9 , further comprising providing 40% fractional bandwidth while relying on a physical linear dispersion of transmission lines of a lossless output combiner.

14 . The method of claim 9 , further comprising providing a constant output at peak power over an entire bandwidth.

15 . The method of claim 9 , further comprising:

maintaining a predetermined impedance at the common load for the main transistor and the auxiliary transistor as an output power of the dual transistor power amplifier varies from a peak output power to a back-off output (OBO) power.

16 . The method of claim 15 , further comprising providing, by the common load, a DC drain bias for dual transistor the power amplifier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2025
From: ROBLIN, PATRICK; MIKRUT, DOMINIC
To: OHIO STATE INNOVATION FOUNDATION
Reel/Frame 072617/0303 →
Continuity (2)
Provisional Application 63238913 · Aug 31, 2021
Related Publication 20250219585A1 · Jul 3, 2025
References Cited (11)
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