Wafer image denoising and contour extraction for manufacturing process calibration
This application discloses a computing system to obtain a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design. The computing system can implement an unsupervised deep learning algorithm to process the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image. The computing system can extract contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device without use of the layout design or a mask design. The computing system can calibrate the layout design or the mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.
1 . A method comprising:
obtaining, by a computing system, a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design;
processing, by the computing system, the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image, wherein the processing of the wafer image determines a noisy pixel distribution within the wafer image and a structure pixel distribution within the wafer image, utilizes the noisy pixel distribution and the structure pixel distribution within the wafer image to identify the presence of stochastic noise in the wafer image, and removes at least some noise from the wafer image by removing at least a portion of the stochastic noise from the wafer image based on the noisy pixel distribution and the structure pixel distribution within the wafer image; and
extracting, by the computing system, contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device.
2 . The method of claim 1 , further comprising calibrating, by the computing system, the layout design or a mask design describing the one or more lithographic masks based, at least in part, on the contours extracted based on the denoised wafer image.
3 . The method of claim 1 , wherein extracting the contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device further comprises:
measuring at least one of areas and lengths of the contours extracted from the denoised wafer image;
identifying one or more of the contours extracted from the denoised wafer image have areas or lengths fall below of threshold area or length; and
removing the identified contours from the extracted from the contours extracted from the denoised wafer image.
4 . The method of claim 1 , wherein extracting the contours corresponding to the physical structures of the electronic device based on the denoised wafer image is performed without use of the layout design or a mask design describing the one or more lithographic masks.
5 . The method of claim 1 , wherein the computing system is configured to implement an unsupervised deep learning algorithm to remove at least some noise from the wafer image.
6 . The method of claim 1 , wherein the computing system is configured to implement a deep learning algorithm to perform the extraction of the contours from the denoised wafer image.
7 . The method of claim 1 , further comprising:
comparing, by the computing system, contours extracted from the wafer image to the contours extracted from the denoised wafer image; and
performing, by the computing system, a validation of the contours extracted from the denoised wafer image based on the comparison.
8 . A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to:
obtain a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design;
process the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image, wherein the processing of the wafer image determines a noisy pixel distribution within the wafer image and a structure pixel distribution within the wafer image, utilizes the noisy pixel distribution and the structure pixel distribution within the wafer image to identify the presence of stochastic noise in the wafer image, and removes at least some noise from the wafer image by removing at least a portion of the stochastic noise from the wafer image based on the noisy pixel distribution and the structure pixel distribution within the wafer image; and
extract contours corresponding to the physical structures of the electronic device based, at least in part, on the denoised wafer image of the electronic device.
9 . The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to calibrate the layout design or a mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.
10 . The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:
measuring at least one of areas and lengths of the contours extracted from the denoised wafer image;
identifying one or more of the contours extracted from the denoised wafer image have areas or lengths fall below of threshold area or length; and
removing the identified contours from the extracted from the contours extracted from the denoised wafer image.
11 . The system of claim 8 , wherein extracting the contours corresponding to the physical structures of the electronic device from the denoised wafer image is performed without use of the layout design or a mask design describing the one or more lithographic masks.
12 . The system of claim 8 , wherein the computing system is configured to implement an unsupervised deep learning algorithm to remove at least some noise from the wafer image.
13 . The system of claim 8 , wherein the computing system is configured to implement a deep learning algorithm to perform the extraction of the contour from the denoised wafer image.
14 . An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
obtaining a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design;
processing the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image, wherein the processing of the wafer image determines a noisy pixel distribution within the wafer image and a structure pixel distribution within the wafer image, utilizes the noisy pixel distribution and the structure pixel distribution within the wafer image to identify the presence of stochastic noise in the wafer image, and removes at least some noise from the wafer image by removing at least a portion of the stochastic noise from the wafer image based on the noisy pixel distribution and the structure pixel distribution within the wafer image;
extracting contours corresponding to the physical structures of the electronic device based, at least in part, on the denoised wafer image of the electronic device.
15 . The apparatus of claim 14 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising calibrating the layout design or a mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.
16 . The apparatus of claim 14 , wherein extracting the contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device further comprises:
measuring at least one of areas and lengths of the contours extracted from the denoised wafer image;
identifying one or more of the contours extracted from the denoised wafer image have areas or lengths fall below of threshold area or length; and
removing the identified contours from the extracted from the contours extracted from the denoised wafer image.
17 . The apparatus of claim 14 , wherein extracting the contours corresponding to the physical structures of the electronic device from the denoised wafer image is performed without use of the layout design or a mask design describing the one or more lithographic masks.
18 . The apparatus of claim 14 , wherein the computing system is configured to implement an unsupervised deep learning algorithm to remove at least some noise from the wafer image.
19 . The apparatus of claim 14 , wherein the computing system is configured to implement a deep learning algorithm to perform the extraction of the contour from the denoised wafer image.
20 . The apparatus of claim 14 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:
comparing contours extracted from the wafer image to the contours extracted from the denoised wafer image; and
performing a validation of the contours extracted from the denoised wafer image based on the comparison.