Memory device and method of manufacturing memory device
According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction.
1 . A memory device comprising:
a substrate;
a first bit line provided above the substrate;
a first transistor including:
a first semiconductor layer provided between the substrate and the first bit line;
a first gate electrode facing a side surface of the first semiconductor layer; and
a first gate insulating layer provided between the first semiconductor layer and the first gate electrode;
a first memory element provided between the first transistor and the substrate;
a first word line including a first conductive layer coupled to the first gate electrode;
a second transistor including:
a second semiconductor layer provided between the substrate and the first bit line;
a second gate electrode facing a side surface of the second semiconductor layer; and
a second gate insulating layer provided between the second semiconductor layer and the second gate electrode;
a second memory element provided between the second transistor and the substrate;
a second word line that is adjacent to the first word line in a first direction in parallel to a surface of the substrate and that includes a second conductive layer coupled to the second gate electrode;
a second bit line provided above the substrate;
a third transistor including:
a third semiconductor layer provided between the substrate and the second bit line;
a third gate electrode facing a side surface of the third semiconductor layer; and
a third gate insulating layer provided between the third semiconductor layer and the third gate electrode; and
a third memory element provided between the third transistor and the substrate, wherein
the second semiconductor layer is adjacent to the first semiconductor layer in a second direction that is in parallel to the surface of the substrate and intersects the first direction, and
the second transistor is provided at a position different from a position of the first transistor and a position of the third transistor in the first direction and is provided between the first transistor and the third transistor in a third direction that is in parallel to the surface of the substrate, intersects the first and second directions, and the first word line extends in the third direction.
2 . The memory device according to claim 1 , wherein the second semiconductor layer is adjacent to the first conductive layer in the first direction.
3 . The memory device according to claim 1 , wherein the first semiconductor layer includes an oxide semiconductor layer.
4 . The memory device according to claim 1 , wherein the first conductive layer has a first dimension in the first direction,
the first semiconductor layer has a second dimension in the first direction,
the first gate electrode has a third dimension in the first direction,
the first gate insulating layer has a fourth dimension in the first direction, and
the first dimension is smaller than a sum of the second dimension, the third dimension, and the fourth dimension.
5 . The memory device according to claim 1 , wherein
the third gate electrode is coupled to the first gate electrode with the first conductive layer intervening therebetween,
the first conductive layer has a first dimension in the first direction,
the first semiconductor layer has a second dimension in the first direction,
the first gate electrode has a third dimension in the first direction,
the first gate insulating layer has a fourth dimension in the first direction, and
the first dimension is smaller than a sum of the second dimension, the third dimension, and the fourth dimension.
6 . The memory device according to claim 1 , wherein the first memory element includes:
a first electrode provided between the first semiconductor layer and the substrate;
a second electrode facing a side surface of the first electrode; and
an insulating layer provided between the first electrode and the second electrode.
7 . The memory device according to claim 1 , wherein the first semiconductor layer includes:
a first source/drain region;
a second source/drain region provided above the first source/drain region; and
a channel region provided between the first source/drain region and the second source/drain region, and
the first gate electrode covers a first surface of the channel region with the first gate insulating layer intervening therebetween.
8 . The memory device according to claim 1 , further comprising a first circuit provided on the substrate below the first memory element.
9 . The memory device according to claim 1 , wherein the first bit line includes:
a first portion extending in the second direction; and
a second portion extending in a third direction that is in parallel to the surface of the substrate and that intersects the second direction.
10 . The memory device according to claim 9 , wherein a fifth dimension of the first portion in the second direction is twice or more greater than a six dimension in the second direction that couples a center of the first semiconductor layer and a center of the second semiconductor layer.
11 . The memory device according to claim 1 , wherein the third transistor is adjacent to the first transistor in the third direction.