Crack detection integrity check

1. A method of testing an integrated circuit die for presence of a crack, the method comprising:

performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:

a) lowering a tip of a first manipulator arm to contact and pick up a given integrated circuit die of the plurality of integrated circuit die of the wafer;

b) flipping the given integrated circuit die such that a surface of the given integrated circuit die facing the wafer now faces a different direction, and transferring the given integrated circuit die to a tip of a second manipulator arm;

c) applying pressure from the second manipulator arm to the given integrated circuit die such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the given integrated circuit die for making an electrical connection to a crack detector on the given integrated circuit die;

d) performing a conductivity test on the crack detector using the pogo pins; and

e) if the conductivity test indicates a lack of presence of a crack in the given integrated circuit die, then using the second manipulator arm to continue processing of the given integrated circuit die for packaging.

2. The method of claim 1 , wherein the assembly process further comprises a step of: f) if the conductivity test indicates presence of a crack in the given integrated circuit die, then using the second manipulator arm to place the given integrated circuit die into a discard bin.

3. The method of claim 2 , wherein the presence of the crack in the given integrated circuit die indicates that the crack extends from a periphery of the given integrated circuit die, through a die seal ring of the given integrated circuit die, and into an integrated circuit region of the given integrated circuit die.

4. The method of claim 1 , wherein the assembly process further comprises steps of:

g) sealing a package; and

h) storing the package.

5. The method of claim 1 , further comprising performing front end integrated circuit fabrication processes to produce the wafer having the plurality of integrated circuit die, prior to performing the back end integrated circuit fabrication processes; and wherein performing the front end integrated circuit fabrication processes includes:

fabricating the wafer to include the plurality of integrated circuit die;

performing a wafer sort operation including testing of the plurality of integrated circuit die, the testing of the plurality of integrated circuit die including, for each of the plurality of integrated circuit die, performing a conductivity test of the crack detector of an integrated circuit chain using test apparatus to determine presence of a crack in an integrated circuit die extending from a periphery of that integrated circuit die, through a die seal ring of that integrated circuit die, and into an integrated circuit region of that integrated circuit die; and marking those of the plurality of integrated circuit die for which the conductivity test of the crack detector determines presence of a crack.

6. The method of claim 1 , wherein picking up the given integrated circuit die of the wafer is performed by applying suction from the tip of the first manipulator arm to the given integrated circuit die.

7. A manipulator device for performing die pickup operations in integrated circuit manufacture, the manipulator device comprising:

a manipulator body having a cavity extending therethrough;

a manipulator tip associated with the manipulator body and having a first cavity extending therethrough in fluid communication with the cavity of the manipulator body such that suction applied to a distal end of the cavity of the manipulator body results in suction into a distal end of the first cavity, the manipulator tip also having a second cavity extending therethrough and a third cavity extending therethrough; and

a tester jig between the manipulator body and manipulator tip, the tester jig including a first electrically conductive probe extending through the second cavity to protrude from a distal end of the manipulator tip and a second electrically conductive probe extending through the third cavity to protrude from the distal end of the manipulator tip.

8. The manipulator device of claim 7 , wherein the manipulator body has a narrowed male end adjacent the manipulator tip; and wherein the manipulator tip has an enlarged female end receiving the narrowed male end of the manipulator body.

9. The manipulator device of claim 7 , further comprising:

a first conductor directly electrically connected to the first electrically conductive probe, and extending through the manipulator tip and the manipulator body to protrude from an exterior surface of the manipulator body; and

a second conductor directly electrically connected to the second electrically conductive probe, and extending through the manipulator tip and the manipulator body to protrude from the exterior surface of the manipulator body.

10. The manipulator device of claim 9 , further comprising a test interface coupled to the first and second conductors, the test interface configured to perform a continuity test to determine whether a high electrical conductivity is present between the first and second electrically conductive probes, the high electrical conductivity indicating a lack of a crack in an integrated circuit region of an integrated circuit die being tested by the manipulator device.

11. The manipulator device of claim 9 , further comprising a test interface coupled to the first and second conductors, the test interface configured to perform a continuity test to determine whether a low electrical conductivity is present between the first and second electrically conductive probes, the low electrical conductivity indicating a crack in the integrated circuit region of the integrated circuit die being tested by the manipulator device.

12. The manipulator device of claim 7 , further comprising a suction source in fluid communication with the cavity of the manipulator body so as to provide suction upward into the distal end of the first cavity of the manipulator tip.

13. A method of testing an integrated circuit die for presence of a crack, the method comprising:

performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:

a) lowering a tip of a first manipulator arm to contact a given integrated circuit die of the plurality of integrated circuit die of the wafer such that pogo pins extending from the tip make electrical contact with conductive areas on the given integrated circuit die so that the pogo pins are electrically connected to a crack detector on the given integrated circuit die;

b) picking up the given integrated circuit die using the first manipulator arm; and

c) performing a conductivity test on the crack detector using the pogo pins.

14. The method of claim 13 , wherein the presence of the crack in the given integrated circuit die indicates that the crack extends from a periphery of the given integrated circuit die, through a die seal ring of the given integrated circuit die, and into an integrated circuit region of the given integrated circuit die.

15. The method of claim 13 , wherein picking up the given integrated circuit die of the wafer is performed by applying suction from the tip of the first manipulator arm to the given integrated circuit die.

16. A method of testing an integrated circuit die for presence of a crack, the method comprising:

performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:

a) lowering a tip of a first manipulator arm to contact and pick up a given integrated circuit die of the plurality of integrated circuit die of the wafer;

b) flipping the given integrated circuit die such that a surface of the given integrated circuit die facing the wafer now faces a different direction, and transferring the given integrated circuit die to a tip of a second manipulator arm;

c) applying pressure from the second manipulator arm to the given integrated circuit die such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the given integrated circuit die so that the pogo pins are electrically connected to a crack detector on the given integrated circuit die; and

d) performing a conductivity test on the crack detector using the pogo pins.

17. The method of claim 16 , wherein the assembly process further comprises a step of: e) if the conductivity test indicates presence of a crack in the given integrated circuit die, then using the second manipulator arm to place the given integrated circuit die into a discard bin.

18. The method of claim 16 , wherein the presence of the crack in the given integrated circuit die indicates that the crack extends from a periphery of the given integrated circuit die, through a die seal ring of the given integrated circuit die, and into an integrated circuit region of the given integrated circuit die.

19. The method of claim 16 , wherein picking up the given integrated circuit die of the wafer is performed by applying suction from the tip of the first manipulator arm to the given integrated circuit die.