Method of manufacturing a field effect transducer

1. A method of manufacturing a field effect transducer (FET), the method comprising:

providing a FET base structure comprising a substrate, a drain, and a source;

providing a channel layer on the FET base structure, the channel layer being electrically connected to the drain and the source; and

providing a first layer on the FET base structure,

the first layer comprising a one-dimensional material or a two-dimensional material and overlaying a first surface of the channel layer, the drain, and the source so as to form a sensing surface of the FET, wherein the sensing surface is opposite the first surface;

wherein

providing the channel layer on the FET base structure and providing the first layer on the FET base structure comprise providing a single body onto the FET base structure, the single body being Formed prior to assembly on the FET base structure and having the channel layer and the first layer.

2. The method of claim 1 , wherein providing the single body comprises forming the single body and subsequently transferring the single body onto the FET base structure.

3. The method of claim 2 , wherein forming the single body and subsequently transferring the single body, onto the FET base structure comprise:

forming the channel layer;

subsequently providing the first layer on the channel layer; and

subsequently transferring the channel layer and the first layer onto the PET base structure.

4. The method of claim 3 , wherein subsequently providing the first layer on the channel layer comprises forming the first layer on the channel layer.

5. The method of claim 4 , wherein the channel layer comprises grapheme and the first layer comprises hexagonal boron nitride (hBN), and wherein forming the first layer on the channel layer comprises forming hBN on a surface of the graphene.

6. The method of claim 3 , wherein the single body further has a supporting body, and Wherein during the subsequently transferring the channel layer and the first layer onto the FET base structure, the channel layer and first layer are supported on the supporting body; and

wherein the method further comprises separating the supporting body from the channel layer and first layer after the channel layer and first layer have been provided on the FET base structure.

7. The method of claim 6 , wherein forming the channel layer comprises forming the channel layer on a temporary substrate and subsequently transferring the channel layer from the temporary substrate to the supporting body.

8. The method of claim 2 , further comprising providing a second layer on the FET base structure, the second layer comprising a one-dimensional material or a two-dimensional material;

wherein the second layer is arranged on a second surface of the channel layer, the second surface opposite the first surface.

9. The method of claim 8 , wherein providing the second layer comprises forming the second layer and subsequently transferring the second layer onto the FET base structure.

10. The method of claim 9 , wherein forming the single body and subsequently transferring the single body onto the FET base structure, and providing the second layer comprise:

forming the channel layer;

subsequently providing the second layer on the channel layer; and

subsequently transferring the channel layer and the second layer onto the FET base structure.

11. The method of claim 10 , wherein subsequently providing the second layer on the channel layer comprises forming the second layer on the channel layer.

12. The method of claim 9 , wherein forming the single body and subsequently transferring the single body onto the PET base structure, and providing the second layer comprise:

forming the channel layer;

subsequently providing the first layer and the second layer on the channel layer; and

subsequently transferring the channel layer, the first layer, and the second layer onto the FET base structure.

13. The method of claim 12 , wherein providing the first layer and the second layer on the channel layer comprises forming the first layer and the second layer on the channel layer.

14. The method of claim 13 , wherein the channel layer comprises graphene, the first layer comprises hexagonal boron nitride, and the second layer comprises hexagonal boron nitride.

15. The method of claim 1 , wherein providing the FET base structure comprises forming the FET base structure using a complementary metal-oxide-semiconductor (CMOS) fabrication process.

16. The method of claim 1 , wherein the FET base structure further comprises a gate comprising a gate electrode and a gate dielectric layer, and wherein the first layer is arranged on the FET base structure above the gate.

17. The method of claim 1 , wherein providing the FET base structure comprises:

providing the substrate, the substrate comprising a Si substrate; and

providing the drain and source on the substrate.

18. The method of claim 1 , wherein providing the FET base structure comprises:

providing the substrate, the substrate comprising a polymeric substrate; and

providing the drain and source on the substrate.

19. The method of claim 1 , further comprising modifying the first layer by at least one of functionalising the first layer and doping the first layer, wherein modifying the first layer is carried out after the channel layer is provided on the FET base structure.

20. The method of claim 1 , wherein the one-dimensional material or the two-dimensional material is selected from graphene, hexagonal boron-nitride, carbon nano-tubes, or a combination thereof.