IP Library › Granted Patent US 12,014,062
Granted Patent B2
US 12,014,062 · App. 17/830,138 · Granted Jun 18, 2024

Storage device and operating method thereof

Inventor: Hyun Tae Kim (Icheon-si, KR)
Assignee: SK HYNIX INC.
G06F3/064G06F3/0604G06F3/0634G06F3/0659G06F3/0673
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,014,062
App. No.
17/830,138
Granted
Jun 18, 2024
Kind
B2
Abstract

A storage device may include: a storage comprising a plurality of memory blocks of memory cells for storing data; and a controller in communication with the storage to control operations of the storage and configured, in response to a write request from an external device to write data to the storage, to generate a first zone including one or more memory blocks and sequentially store the data from a first storage position of the first zone, and further configured, in response to a modification request from the external device to modify the data stored in the first zone, to identify a target memory block corresponding to the modification request and rewrite data to the target memory block.

Claims (30)

1. A storage device comprising:

a storage comprising a plurality of memory blocks of memory cells for storing data; and

a controller in communication with the storage to control operations of the storage and configured, in response to a write request from an external device to write data to the storage, to generate a first zone including one or more memory blocks and sequentially store the data from a first storage position of the first zone, and further configured, in response to a modification request from the external device to modify the data stored in the first zone, to identify a target memory block corresponding to the modification request and rewrite data to the target memory block, wherein the controller further includes a zone division circuit configured, in response to the modification request for the first zone having a closed state, to divide the first zone into one or more sub-zones, each sub-zone corresponding to a memory block, and change a state of the target memory block from a closed state to an open state; and

a zone combining circuit configured, in response to a completion of the modification request, to combine the one or more sub-zones.

2. The storage device according to claim 1 , wherein the controller is further configured to reset the target memory block, and set a write pointer to point out a first storage position of the target memory block.

3. The storage device according to claim 1 , wherein the controller is further configured to change a state of the target memory block from the open state to the closed state after a completion of the rewrite operation.

4. The storage device according to claim 1 , wherein the controller is further configured to set a write pointer to point out a last data storage position of the first zone after a completion of the rewrite operation.

5. The storage device according to claim 1 , wherein each memory block corresponding to a minimum unit that data is erased at one time.

6. The storage device according to claim 1 , wherein the controller stores a zone management table including information, for each zone, an identifier (ID), a start logical address, a capacity indicating a total size of an area available for a write operation, a state indicating whether a corresponding zone is in the open state or the closed state, or a write pointer (WP) indicating an address of a particular position in a corresponding zone.

7. The storage device of claim 1 , wherein the storage includes a nonvolatile memory device.

8. The storage device of claim 1 , wherein the memory cells operate as a single level cell storing 1-bit data or a multi-level cell storing 2 or more-bit data.

9. The storage device of claim 1 , wherein the write request includes a write address, write data, and a size of the write data.

10. The storage device of claim 1 , wherein the controller is further configured to assign an identifier (ID) to the first zone.

11. A method of operating a storage device including a plurality of memory blocks of memory cells for storing data and a controller that controls operations of the storage device, comprising:

generating, by the controller, a first zone including one or more memory blocks in response to a write request received from an external device;

storing, by the controller, data such that the data is sequentially stored from a first storage position of the first zone, and closing the first zone;

dividing, by the controller, in response to a modification request from the external device to modify the data stored in the first zone, the first zone into one or more sub-zones, each sub-zone corresponding to a memory block, to identify a target memory block;

changing, by the controller, a state of the target memory block from a closed state to an open state;

rewriting, by the controller, data to the target memory block; and

combining, by the controller, in response to a completion of the modification request, the one or more sub-zones.

12. The method according to claim 11 , wherein the changing of the state of the target memory block comprises:

resetting the target memory block; and

setting a write pointer to point out a first storage position of the target memory block.

13. The method according to claim 11 , further comprising, after the rewriting of the data: changing the state of the target memory block to the closed state.

14. The method according to claim 11 , further comprising, after the rewriting of the data: setting a write pointer to point out a last data storage position of the first zone.

15. The method of claim 11 , wherein the storage device includes a nonvolatile memory device.

16. The method of claim 11 , wherein the memory cells operate as a single level cell storing 1-bit data or a multi-level cell storing 2 or more-bit data.

17. The method of claim 11 , wherein the write request includes a write address, write data, and a size of the write data.

18. The method of claim 11 , further comprising, after the generating of the first zone, assigning an identifier (ID) to the first zone.

19. The operating method of claim 11 , wherein each memory block corresponding to a minimum unit that data is erased at one time.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2022
From: KIM, HYUN TAE
To: SK HYNIX INC.
Reel/Frame 060075/0857 →
Priority Claims (1)
KR 10-2021-0144557 · Oct 27, 2021 · national
Continuity (1)
Related Publication 20230129727A1 · Apr 27, 2023