Signal routing between memory die and logic die

1. A method, comprising:

activating, via control circuitry coupled to a memory die, a row of the memory die;

responsive to activating the row, latching a first plurality of signals in a sense amplifier stripe of the memory die;

routing, via a transceiver, a second plurality of signals from the sense amplifier stripe to a logic die which is bonded to the memory die via a wafer-on-wafer bond; and

receiving a third plurality of signals from the logic die at the sense amplifier stripe to store the third plurality of signals in the memory die.

2. The method of claim 1 , further comprising configuring, via the control circuitry, a plurality of multiplexers to route the second plurality of signals from the sense amplifier stripe to a global data bus of the memory die.

3. The method of claim 2 , further comprising configuring the transceiver to route the second plurality of signals to the logic die concurrently with a routing of the second plurality of signals to the global data bus.

4. The method of claim 1 , further comprising, responsive to the transceiver routing the second plurality of signals, refraining from activating a global data bus of the memory die.

5. The method of claim 1 , further comprising, routing the second plurality of signals to a processing resource of the logic die.

6. A method, comprising:

activating a plurality of rows of memory cells of a memory die;

responsive to activating the plurality of rows of memory cells, latching a first plurality of signals in a plurality of sense amplifiers;

multiplexing a second plurality of signals provided by the plurality of sense amplifiers onto a plurality of local input/output (LIO) lines; and

routing, via a respective transceiver coupled to each of the plurality of LIO lines, a multiplexed signal, of the second plurality of multiplexed signals, from a corresponding LIO line to a logic die bonded to the memory die via a wafer-on-wafer bond.

7. The method of claim 6 , further comprising activating the plurality of rows each of which corresponds to a different tile from a plurality of tiles of the memory die.

8. The method of claim 6 , further comprising activating the plurality of rows which are similarly located in each of a plurality of tiles of the memory die.

9. The method of claim 6 , further comprising latching the first plurality of signals in sense amplifier stripes comprising the plurality of sense amplifiers.

10. The method of claim 9 , further comprising multiplexing the second plurality of signals on a sense amplifier stripe basis.

11. The method of claim 9 , further comprising receiving, via the respective transceiver coupled to each of the plurality of LIO lines, a third plurality of signals from the logic die to the corresponding LIO line.

12. The method of claim 6 , further comprising activating the plurality of rows concurrently.

13. The method of claim 6 , further comprising routing the multiplexed signal from the corresponding LIO line of the memory die to different LIO line of the logic die.

14. An apparatus, comprising:

a memory die;

a logic die bonded to the memory die via a wafer-on-wafer bond;

a plurality of transceivers coupled to a plurality of sense amplifier stripes of the memory die; and

control circuitry coupled to the memory die and configured to:

activate a plurality of rows of the memory die; and

responsive to activating the plurality of rows, latch a first plurality of signals in the sense amplifier stripes;

wherein the plurality of transceivers are configured to;

receive control signals from a deep learning accelerator (DLA) of the logic die to route data corresponding to the first plurality of signals from the plurality of sense amplifier stripes to the logic die;

route a second plurality of signals from the plurality of sense amplifier stripes to the logic die.

15. The apparatus of claim 14 , wherein the plurality of transceivers are configured to, responsive to receipt of the control signals, route the data concurrently.

16. The apparatus of claim 14 , wherein each transceiver from the plurality of transceivers is configured, responsive to receipt of the control signals, to route a different portion of the data concurrently with a routing of other portions of the data.

17. A method, comprising:

activating, via control circuitry coupled to a memory die, a row of the memory die;

responsive to activating the row, latching a first plurality of signals in a sense amplifier stripe of the memory die;

routing, via a transceiver, a second plurality of signals from the sense amplifier stripe to a logic die which is bonded to the memory die via a wafer-on-wafer bond; and

responsive to the transceiver routing the second plurality of signals, refraining from activating a global data bus of the memory die.