ESD protection circuit
An electrostatic discharge (ESD) protection circuit is provided to minimize ESD damage to an internal circuit in a CDM model. The ESD protection circuit includes two stages of discharging circuits that are coupled to an IO pin and the internal circuit, a first power clamp circuit, and a second power clamp circuit. The first power clamp circuit is electrically connected to a power rail and a ground rail to discharge a part of a current to the ground, and the second power clamp circuit is electrically connected to a second-stage discharging circuit and the ground rail, so that the other part of the current is discharged to the ground through the second power clamp circuit.
1. An electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit comprises:
a first-stage discharging circuit that is electrically connected to an IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to a protected circuit, and the ground rail; and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
wherein
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.
2. The ESD protection circuit according to claim 1 , wherein
the second power clamp circuit comprises a first PNP transistor,
a collector of the first PNP transistor is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
an emitter of the first PNP transistor is electrically connected to the ground rail.
3. The ESD protection circuit according to claim 1 , wherein
the second power clamp circuit comprises a first Zener diode,
a positive electrode of the first Zener diode is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
a negative electrode of the first Zener diode is electrically connected to the ground rail.
4. The ESD protection circuit according to claim 1 , wherein
the ESD protection circuit further comprises an inter-stage impedance,
the first-stage discharging circuit comprises a first pull-up discharging component and a first pull-down discharging component, wherein
a first terminal of the first pull-up discharging component is electrically connected to the power rail,
a second terminal of the first pull-up discharging component is electrically connected to the IO pin, a first terminal of the first pull-down discharging component, and a first terminal of the inter-stage impedance, and
a second terminal of the first pull-down discharging component is electrically connected to the ground rail, and
the second-stage discharging circuit comprises a second pull-up discharging component and a second pull-down discharging component, wherein
a first terminal of the second pull-up discharging component is electrically connected to the second power clamp circuit,
a second terminal of the second pull-up discharging component is electrically connected to the protected circuit, a first terminal of the second pull-down discharging component, and a second terminal of the inter-stage impedance, and
a second terminal of the second pull-down discharging component is electrically connected to the ground rail.
5. The ESD protection circuit according to claim 4 , wherein the first pull-up discharging component, the first pull-down discharging component, the second pull-up discharging component, and the second pull-down discharging component each comprise a diode or a silicon controlled rectifier.
6. The ESD protection circuit according to claim 1 , wherein the first power clamp circuit comprises a second Zener diode.
7. The ESD protection circuit according to claim 1 , wherein the first power clamp circuit comprises a second PNP transistor.
8. The ESD protection circuit according to claim 1 , wherein the first power clamp circuit comprises a second RC power clamp circuit.
9. An apparatus, comprising a chip and an electrostatic discharge (ESD) protection circuit, wherein
the chip comprises an IO pin and a protected circuit, and
the ESD protection circuit comprises:
a first-stage discharging circuit that is electrically connected to the IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to the protected circuit, and the ground rail; and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.
10. The apparatus according to claim 9 , wherein
the second power clamp circuit comprises a first PNP transistor,
a collector of the first PNP transistor is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
an emitter of the first PNP transistor is electrically connected to the ground rail.
11. The apparatus according to claim 9 , wherein
the second power clamp circuit comprises a first Zener diode,
a positive electrode of the first Zener diode is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
a negative electrode of the first Zener diode is electrically connected to the ground rail.
12. The apparatus according to claim 9 , wherein
the ESD protection circuit further comprises an inter-stage impedance,
the first-stage discharging circuit comprises a first pull-up discharging component and a first pull-down discharging component, wherein
a first terminal of the first pull-up discharging component is electrically connected to the power rail,
a second terminal of the first pull-up discharging component is electrically connected to the IO pin, a first terminal of the first pull-down discharging component, and a first terminal of the inter-stage impedance, and
a second terminal of the first pull-down discharging component is electrically connected to the ground rail, and
the second-stage discharging circuit comprises a second pull-up discharging component and a second pull-down discharging component, wherein
a first terminal of the second pull-up discharging component is electrically connected to the second power clamp circuit,
a second terminal of the second pull-up discharging component is electrically connected to the protected circuit, a first terminal of the second pull-down discharging component, and a second terminal of the inter-stage impedance, and
a second terminal of the second pull-down discharging component is electrically connected to the ground rail.
13. The apparatus according to claim 12 , wherein the first pull-up discharging component, the first pull-down discharging component, the second pull-up discharging component, and the second pull-down discharging component each comprise a diode or a silicon controlled rectifier.
14. The apparatus according to claim 9 , wherein the first power clamp circuit comprises:
a second Zener diode,
a second PNP transistor, or
a second RC power clamp circuit.