IP Library › Granted Patent US 12,610,756
Granted Patent B2
US 12,610,756 · App. 17/832,809 · Granted Apr 21, 2026

Method of manufacturing nitride semiconductor device

Inventors: Takashi Okawa (Nisshin, JP); Kenta Watanabe (Nisshin, JP)
Assignees: DENSO CORPORATION; TOYOTA JIDOSHA KABUSHIKI KAISHA; MIRISE Technologies Corporation
H01L21/02579C30B25/02C30B29/403C30B29/406C30B29/68C30B33/02H01L21/0254H01L21/0262
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Quick Facts
Patent No.
US 12,610,756
App. No.
17/832,809
Granted
Apr 21, 2026
Kind
B2
Abstract

A manufacturing method of a nitride semiconductor device includes: introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region; forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region; and performing an anneal treatment in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer.

Claims (25)

1 . A manufacturing method of a nitride semiconductor device, the manufacturing method comprising:

introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region;

forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region, the second nitride semiconductor layer being coherently grown and formed, and the p type impurity introduction region being formed at a position exposed on the upper surface of the first nitride semiconductor layer;

performing an anneal treatment after the second nitride semiconductor layer is formed on the first nitride semiconductor layer and on the p type impurity introduction region at the position exposed on the upper surface of the first nitride semiconductor layer in a state where at least a part of the p type impurity introduction region is disposed in a two-dimensional electron gas layer of the first nitride semiconductor layer; and

removing the second nitride semiconductor layer from the first nitride semiconductor layer after performing the anneal treatment, wherein:

in the forming the second nitride semiconductor layer, the second nitride semiconductor layer is formed by stacking nitride semiconductor layers having different composition ratios,

the first nitride semiconductor layer is made of GaN,

the second nitride semiconductor layer is comprised of a lower second nitride semiconductor layer formed of InAlN that is adjacent to the first nitride semiconductor layer and an upper second nitride semiconductor layer formed of AlGaN and stacked on top of the lower second nitride semiconductor layer,

an upper layer portion of the first nitride semiconductor layer becomes an n type region;

at least a part of the p type impurity introduction region is disposed in the n type region of the first nitride semiconductor layer; and

the anneal treatment is performed in a state where

the upper layer portion of the first nitride semiconductor layer is the n type region, and

the maximum concentration of the p type impurity introduced into the p type impurity introduction region is adjusted to be smaller than the maximum charge density in the two-dimensional electron gas layer.

2 . The manufacturing method of the nitride semiconductor device according to claim 1 , wherein:

in the forming of the second nitride semiconductor layer, the second nitride semiconductor layer is formed so as to increase a composition ratio of aluminum from a first nitride semiconductor layer side toward an outermost surface.

3 . The manufacturing method of the nitride semiconductor device according to claim 2 , wherein:

an annealing temperature in the performing of the anneal treatment is disposed between 1300° C. and 1500° C.

4 . The manufacturing method of the nitride semiconductor device according to claim 1 , wherein:

in the forming of the second nitride semiconductor layer, the second nitride semiconductor layer is formed by a MOCVD technique.

5 . The manufacturing method of the nitride semiconductor device according to claim 1 , wherein:

removing the second nitride semiconductor layer from the first nitride semiconductor layer includes removing the entire second nitride semiconductor layer.

6 . The manufacturing method of the nitride semiconductor device according to claim 1 , wherein:

introducing the p type impurity comprises using an ion implantation technique to implant the p type impurity into the first nitride semiconductor layer.

7 . The manufacturing method of the nitride semiconductor device according to claim 6 , wherein:

introducing the p type impurity further comprises injecting nitrogen into the p type impurity introduction region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2022
From: OKAWA, TAKASHI; WATANABE, KENTA
To: DENSO CORPORATION; TOYOTA JIDOSHA KABUSHIKI KAISHA; MIRISE TECHNOLOGIES CORPORATION
Reel/Frame 060106/0163 →
Priority Claims (1)
JP 2021-100863 · Jun 17, 2021 · national
Continuity (1)
Related Publication 20220406597A1 · Dec 22, 2022
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