System and method for a single logical IP subnet across multiple independent layer 2 (L2) subnets in a high performance computing environment
Systems and methods for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment. A method can provide, at a computer including one or more microprocessors, a logical device, the logical device being addressed by a layer 3 address, wherein the logical device comprises a plurality of network adapters, each of the network adapters comprising a physical port, and a plurality of switches. The method can arrange the plurality of switches into a plurality of discrete layer 2 subnets. The method can provide a mapping table at the logical device.
1 . A system for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, comprising:
a computer including one or more microprocessors;
a logical device being addressed by a layer 3 address, the logical device comprising a plurality of ports, each of the ports being associated with a unique layer 2 address and being addressed by the layer 3 address of the logical device;
a plurality of layer 2 subnets, each layer 2 subnet comprising at least one switch of a plurality of switches;
wherein each layer 2 subnet comprises at least one connection with the logical device;
wherein, upon receiving a packet addressed to the layer 3 address of the logical device and comprising a first layer 2 address of a destination of the packet, the logical device updates a header of the received packet based upon a lookup of the first layer 2 address of the destination of the packet within a mapping function accessible by the logical device, the updated header comprising a new layer 3 address of the destination within one of the plurality of layer 2 subnets.
2 . The system of claim 1 , wherein each of the plurality of layer two subnets are independent of each other.
3 . The system of claim 1 , wherein each of the at least one connections between each of the layer 2 subnets and the logical device are attached to independent ports at the logical device, each independent port being addressed by the layer 3 address of the logical device.
4 . The system of claim 1 , wherein at least two of the plurality of layer 2 subnets are arranged in a multi-chassis link aggregation scheme.
5 . The system of claim 1 , wherein the logical device comprises a mapping function stored in a memory.
6 . The system of claim 5 , wherein the mapping function updates the header of the received packet based upon a destination media access control address contained in the header of the received packet.
7 . The system of claim 6 , wherein the updated header of the received packet comprises a new destination layer 3 address and a new destination media access control address prior to being routed to one or more of the plurality of layer 2 subnets.
8 . A method for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, comprising:
providing a computer including one or more microprocessors;
providing, at the computer, a logical device being addressed by a layer 3 address, the logical device comprising a plurality of ports, each of the ports being associated with a unique layer 2 address and being addressed by the layer 3 address of the logical device;
providing a plurality of layer 2 subnets, each layer 2 subnet comprising at least one switch of a plurality of switches;
wherein each layer 2 subnet comprises at least one connection with the logical device;
wherein, upon receiving a packet addressed to the layer 3 address of the logical device and comprising a first layer 2 address of a destination of the packet, the logical device updates a header of the received packet based upon a lookup of the first layer 2 address of the destination of the packet within a mapping function accessible by the logical device, the updated header comprising a new layer 3 address of the destination within one of the plurality of layer 2 subnets.
9 . The method of claim 8 , wherein each of the plurality of layer two subnets are independent of each other.
10 . The method of claim 8 , wherein each of the at least one connections between each of the layer 2 subnets and the logical device are attached to independent ports at the logical device, each independent port being addressed by the layer 3 address of the logical device.
11 . The method of claim 8 , wherein at least two of the plurality of layer 2 subnets are arranged in a multi-chassis link aggregation scheme.
12 . The method of claim 8 , wherein the logical device comprises a mapping function stored in a memory.
13 . The method of claim 12 , wherein the mapping function updates the header of the received packet based upon a destination media access control address contained in the header of the received packet.
14 . The method of claim 13 , wherein the updated header of the received packet comprises a new destination layer 3 address and a new destination media access control address prior to being routed to one or more of the plurality of layer 2 subnets.
15 . A non-transitory computer readable storage medium having instructions thereon for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment, which when read and executed by a computer cause the computer to perform a method comprising:
providing, at the computer, the computer comprising one or more microprocessors, a logical device being addressed by a layer 3 address, the logical device comprising a plurality of ports, each of the ports being associated with a unique layer 2 address and being addressed by the layer 3 address of the logical device;
providing a plurality of layer 2 subnets, each layer 2 subnet comprising at least one switch of a plurality of switches;
wherein each layer 2 subnet comprises at least one connection with the logical device;
wherein, upon receiving a packet addressed to the layer 3 address of the logical device and comprising a first layer 2 address of a destination of the packet, the logical device updates a header of the received packet based upon a lookup of the first layer 2 address of the destination of the packet within a mapping function accessible by the logical device, the updated header comprising a new layer 3 address of the destination within one of the plurality of layer 2 subnets.
16 . The non-transitory computer readable storage medium of claim 15 , wherein each of the plurality of layer two subnets are independent of each other.
17 . The non-transitory computer readable storage medium of claim 15 , wherein each of the at least one connections between each of the layer 2 subnets and the logical device are attached to independent ports at the logical device, each independent port being addressed by the layer 3 address of the logical device.
18 . The non-transitory computer readable storage medium of claim 15 , wherein at least two of the plurality of layer 2 subnets are arranged in a multi-chassis link aggregation scheme.
19 . The non-transitory computer readable storage medium of claim 15 , wherein the logical device comprises a mapping function stored in a memory.
20 . The non-transitory computer readable storage medium of claim 19 ,
wherein the mapping function updates the header of the received packet based upon a destination media access control address contained in the header of the received packet; and
wherein the updated header of the received packet comprises a new destination layer 3 address and a new destination media access control address prior to being routed to one or more of the plurality of layer 2 subnets.