IP Library › Granted Patent US 11,948,746
Granted Patent B2
US 11,948,746 · App. 17/833,983 · Granted Apr 2, 2024

Multilayer ceramic capacitor

Inventor: Yasuyuki Shimada (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/012H01G4/1227H01G4/224H01G4/30H01G4/0085
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Quick Facts
Patent No.
US 11,948,746
App. No.
17/833,983
Granted
Apr 2, 2024
Kind
B2
Abstract

A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrodes alternately stacked on one another, and two external electrodes respectively on two end surfaces of the multilayer body. Each of the dielectric layers includes, at a location coincident with an end portion of a respective one of the internal electrodes, a thick-walled portion thicker in a stacking direction than a portion corresponding in position to a middle portion of a main surface of the multilayer body. When viewed in the stacking direction, positions of some of the thick-walled portions of the dielectric layers are out of alignment with positions of a remainder of the thick-walled portions of the dielectric layers.

Claims (26)

1. A multilayer ceramic capacitor comprising:

a multilayer body including a plurality of dielectric layers and a plurality of internal electrodes alternately stacked on one another, two main surfaces facing each other in a stacking direction, two end surfaces facing each other in a length direction orthogonal or substantially orthogonal to the stacking direction, and two side surfaces facing each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the length direction; and

two external electrodes respectively on the two end surfaces of the multilayer body; wherein

each of the plurality of dielectric layers includes, at a location coincident with an end portion of a respective one of the internal electrodes, a thick-walled portion thicker in the stacking direction than a portion of the dielectric layer corresponding in position to a middle portion of the main surface; and

when viewed in the stacking direction, positions of some of the thick-walled portions of the plurality of dielectric layers are out of alignment with positions of a remainder of the thick-walled portions of the plurality of dielectric layers.

2. The multilayer ceramic capacitor according to claim 1 , wherein the thick-walled portions include thick-walled portions which are adjacent to each other in the stacking direction and which are out of alignment with each other when viewed in the stacking direction.

3. The multilayer ceramic capacitor according to claim 1 , wherein

the end portions of the internal electrodes are end portions in the width direction; and

the positions of the thick-walled portions are out of alignment with each other in the width direction.

4. The multilayer ceramic capacitor according to claim 3 , wherein each of the thick-walled portions has a band shape having a width of about 10 μm to about 80 μm in the width direction from an end of the respective one of the internal electrodes, and extends in the length direction.

5. The multilayer ceramic capacitor according to claim 1 , wherein

the end portions of the internal electrodes are end portions in the length direction; and

the positions of the thick-walled portions are out of alignment with each other in the length direction.

6. The multilayer ceramic capacitor according to claim 5 , wherein each of the thick-walled portions has a band shape having a width of about 10 μm to about 80 μm in the length direction from an end of the respective one of the internal electrodes, and extends in the width direction.

7. The multilayer ceramic capacitor according to claim 1 , wherein each thick-walled portion includes a thickest portion that is thicker than any other portion of the thick-walled portion, and a position of the thickest portion is defined as the position of the thick-walled portion.

8. The multilayer ceramic capacitor according to claim 1 , wherein the position of each of the thick-walled portions is coincident with an end of the respective one of the internal electrodes.

9. The multilayer ceramic capacitor according to claim 1 , wherein each thick-walled portion includes a thickest portion that is thicker than any other portion of the thick-walled portion, and the thickest portion is about 1.05 times to about 1.30 times as thick as a portion of the dielectric layer corresponding in position to the middle portion of the main surface.

10. The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body includes an inner layer portion including the plurality of internal electrodes, and outer layer portions sandwiching the inner layer portion in the stacking direction and not including the plurality of internal electrodes.

11. The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body has a dimension in the length direction of about 0.2 mm to about 10 mm, a dimension in the width direction W of about 0.1 mm to about 10 mm, and a dimension in the stacking direction T of about 0.1 mm to about 5 mm.

12. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrodes includes at least one of Ni, Cu, Ag, Pd, Ag—Pd alloy, or Au.

13. The multilayer ceramic capacitor according to claim 1 , wherein a number of the plurality of internal electrodes is 15 to 2000.

14. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of dielectric layers includes BaTiO 3 as a main component.

15. The multilayer ceramic capacitor according to claim 14 , wherein each of the plurality of dielectric layers includes at least one of a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or a rare earth.

16. The multilayer ceramic capacitor according to claim 1 , wherein an interface layer is disposed between each of the plurality of dielectric layers and respective ones of the plurality of internal electrode layers.

17. The multilayer ceramic capacitor according to claim 16 , wherein the interface layer includes Sn.

18. The multilayer ceramic capacitor according to claim 1 , wherein a number of the plurality dielectric layers is 15 to 2000.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: SHIMADA, YASUYUKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 060119/0224 →
Priority Claims (1)
JP 2021-113266 · Jul 8, 2021 · national
Continuity (1)
Related Publication 20230016359A1 · Jan 19, 2023
Cited By (1)
US 12,300,442