Plasma-based barrier layer removal method for increasing peak transconductance while maintaining on-state resistance and related devices

1. A transistor device, comprising:

a semiconductor structure comprising a channel layer and a barrier layer;

source and drain contacts on the semiconductor structure; and

a gate on the semiconductor structure between the source and drain contacts,

wherein a first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness,

wherein a second portion of the barrier layer between the gate and the channel layer comprises a floor of a gate recess and has a second thickness, and

wherein the second thickness is less than a third thickness of the barrier layer at corner portions of the gate recess between the floor and opposing sidewalls of the gate recess.

2. The transistor device of claim 1 , wherein the first thickness is about 150 Å to 300 Å, and the second thickness is about 30 Å to 150 Å.

3. The transistor device of claim 1 , wherein a surface roughness along the floor of the gate recess is less than about 3 Å.

4. The transistor device of claim 1 , wherein the floor of the gate recess defines a length of the gate between the source and drain contacts, and a ratio of the length of the gate to the second thickness is about 10:1 or less.

5. The transistor device of claim 4 , wherein the length of the gate is less than about 100 nanometers (nm).

6. The transistor device of claim 1 , wherein the opposing sidewalls respectively comprise a first portion defining an angle of about 85 degrees to about 95 degrees relative to the floor, and a second portion defining an angle of about 40 degrees to 50 degrees relative to the floor.

7. The transistor device of claim 1 , wherein a peak transconductance (g m ) of the transistor device is about 450 mS/mm to 800 mS/mm, and an on-resistance of the transistor device is about 1.5 Ω-mm to 3 Ω-mm.

8. A transistor device, comprising:

a semiconductor structure comprising a channel layer and a barrier layer; and

source and drain contacts and a gate therebetween on the semiconductor structure,

wherein the barrier layer comprises a gate recess including the gate therein, and wherein a surface roughness along a floor of the gate recess is less than about 3 Angstroms (Å).

9. The transistor device of claim 8 , wherein the barrier layer comprises a gallium-based material.

10. The transistor device of claim 9 , wherein a first thickness of the barrier layer at corner portions of the gate recess adjacent between the floor and opposing sidewalls thereof is greater than a second thickness of the barrier layer at the floor of the gate recess.

11. The transistor device of claim 10 , wherein the opposing sidewalls respectively comprise a first portion defining an angle of about 85 degrees to about 95 degrees relative to the floor, and a second portion defining an angle of about 40 degrees to 50 degrees relative to the floor.

12. The transistor device of claim 10 , wherein a third thickness of a portion of the barrier layer extending between the source or drain contact and the gate is about 1.5 times to 4 times greater than the second thickness, and a ratio of a length of the gate along the floor of the gate recess to the second thickness is about 10:1 or less.

13. A transistor device, comprising:

a semiconductor structure comprising a channel layer and a barrier layer; and

source and drain contacts and a gate therebetween on the semiconductor structure,

wherein a first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness and defines a length of the gate between the source and drain contacts, and a ratio of the length of the gate to the second thickness is about 10:1 or less.

14. The transistor device of claim 13 , wherein the first thickness is about 1.5 times to 4 times greater than the second thickness.

15. The transistor device of claim 14 , wherein the first thickness is about 150 Å to 300 Å, and the second thickness is about 30 Å to 150 Å.

16. The transistor device of claim 13 , wherein the length of the gate is less than about 100 nanometers (nm).

17. The transistor device of claim 13 , wherein a peak transconductance (g m ) of the transistor device is about 450 mS/mm to 800 mS/mm.

18. The transistor device of claim 17 , wherein the channel layer and the barrier layer comprise a gallium-based material.

19. The transistor device of claim 13 , wherein the first thickness is about 1.5 times to 4 times greater than the second thickness.

20. A transistor device, comprising:

a semiconductor structure comprising a channel layer and a barrier layer; and

source and drain contacts and a gate therebetween on the semiconductor structure,

wherein the barrier layer comprises a gate recess including the gate therein, the gate recess comprises opposing sidewalls and a floor therebetween,

and wherein edges of the gate recess between the floor and the opposing sidewalls comprise inclined surfaces, and the floor of the gate recess comprises a substantially planar surface that is between the inclined surfaces.

21. The transistor device of claim 20 , wherein the opposing sidewalls respectively comprise a first portion defining an angle of about 85 degrees to about 95 degrees relative to the floor, and a second portion comprising the inclined surfaces having an angle of about 40 degrees to 50 degrees relative to the floor.

22. The transistor device of claim 20 , wherein a first thickness of the barrier layer at the edges of the gate recess is greater than a second thickness of the barrier layer at the floor of the gate recess therebetween, a third thickness of a portion of the barrier layer extending between the source or drain contact and the gate is about 1.5 times to 4 times greater than the second thickness, and a ratio of a length of the gate along the floor of the gate recess to the second thickness is about 10:1 or less.

23. The transistor device of claim 20 , wherein a surface roughness along the floor of the gate recess is less than about 3 Å.

24. A method of fabricating a transistor device, the method comprising:

providing a semiconductor structure comprising a channel layer and a barrier layer;

performing a looped recess process comprising a plurality of loops to define a gate recess in the barrier layer, wherein each of the loops comprises an adsorption process and a desorption process configured to remove a monolayer of the barrier layer; and

forming a gate in the gate recess.

25. The method of claim 24 , wherein each of the loops comprises the adsorption process and the desorption process with a purge process therebetween, wherein the adsorption process is chlorine-based, the desorption process is argon-based, and the purge process is helium- or nitrogen-based.

26. The method of claim 24 , wherein the looped recess process is a plasma etch process that is performed using an inductively-coupled plasma tool with a peak-to-peak voltage of about 70 V to 110 V.

27. The method of claim 24 , wherein, responsive to performing the looped recess process, a surface roughness along a floor of the gate recess is less than about 3 Å.

28. The method of claim 24 , wherein, responsive to performing the looped recess process, a first thickness of the barrier layer at corner portions of the gate recess between a floor and opposing sidewalls thereof is greater than a second thickness of the barrier layer at the floor of the gate recess.