Memory device with peripheral circuitry which extends under a back end memory array
Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.
1 . An integrated circuit (IC) die comprising:
a first memory array comprising first dynamic random access memory (DRAM) cells, wherein the first memory array extends in a first area of a first horizontal plane, wherein the first area comprises a maximum horizontal range of any memory cells of the first memory array which are in the first horizontal plane, and wherein a first edge of the first area is opposite a second edge of the first area;
a second memory array comprising second DRAM cells, wherein the second memory array extends in a second area of the first horizontal plane, wherein the second area comprises a maximum horizontal range of any memory cells of the second memory array which are in the first horizontal plane, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level; and
a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to:
receive a first signal and a second signal via the first bit line and the second bit line, respectively;
generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells;
wherein:
the first bit line and the second bit line extend from the first array level toward a front end of line (FEOL) of the IC die;
a portion of the first bit line extends vertically through the first horizontal plane at a first location which is external to the first area;
the second edge is between the first location and each of the first edge and the second area;
a portion of the second bit line extends vertically through the first horizontal plane at a second location which is between the first edge and the second area; and
a maximum horizontal range of the differential sense amplifier in a second horizontal plane of the FEOL is within a third area of the second horizontal plane, wherein the third area is within a footprint of the first area.
2 . The IC die of claim 1 , further comprising:
a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level; and
first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
3 . The IC die of claim 2 , wherein the first level selection circuitry is in the footprint of the first area.
4 . The IC die of claim 2 , further comprising:
a fourth memory array comprising fourth DRAM cells, wherein the fourth memory array is in the second array level; and
second level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a fourth bit line, wherein the second level selection circuitry is coupled to the fourth memory array via the fourth bit line, and wherein the second level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
5 . The IC die of claim 4 , wherein the first level selection circuitry and the second level selection circuitry are each in the footprint of the first area.
6 . The IC die of claim 4 , further comprising:
a first word line driver circuit coupled to the second memory array via a first word line; and
a second word line driver circuit coupled to the fourth memory array via a second word line;
wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.
7 . The IC die of claim 6 , wherein, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL; and
wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.
8 . The IC die of claim 6 , wherein first peripheral circuitry of the IC die is to access the first memory array, the second memory array, the third memory array and the fourth memory array;
wherein the first peripheral circuitry is arranged in a first tile area of the FEOL; and
wherein the first tile area forms recess structures each at a respective one of opposite ends of the first tile area.
9 . The IC die of claim 8 , wherein the first peripheral circuitry comprises:
the differential sense amplifier;
the first level selection circuitry;
the second level selection circuitry;
the first word line driver circuit;
the second word line driver circuit; and
a third word line driver circuit coupled to a fifth memory array via a third word line, wherein a third array level of the BEOL comprises the fifth memory array.
10 . A system comprising:
an integrated circuit (IC) die comprising:
a first memory array comprising first dynamic random access memory (DRAM) cells, wherein the first memory array extends in a first area of a first horizontal plane, wherein the first area comprises a maximum horizontal range of any memory cells of the first memory array which are in the first horizontal plane, and wherein a first edge of the first area is opposite a second edge of the first area;
a second memory array comprising second DRAM cells, wherein the second memory array extends in a second area of the first horizontal plane, wherein the second area comprises a maximum horizontal range of any memory cells of the second memory array which are in the first horizontal plane, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level; and
a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to:
receive a first signal via the first bit line, and receive a second signal via the second bit line; and
generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells;
wherein:
the first bit line and the second bit line extend from the first array level toward a front end of line (FEOL) of the IC die;
a portion of the first bit line extends vertically through the first horizontal plane at a first location which is external to the first area;
the second edge is between the first location and each of the first edge and the second area;
a portion of the second bit line extends vertically through the first horizontal plane at a second location which is between the first edge and the second area; and
a maximum horizontal range of the differential sense amplifier in a second horizontal plane of the FEOL, is within a third area of the second horizontal plane, wherein the third area is within a footprint of the first area; and
a display device coupled to the IC die, the display device to display an image based on the bit value.
11 . The system of claim 10 , further comprising:
a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level; and
first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
12 . The system of claim 11 , further comprising:
a fourth memory array;
a first word line driver circuit coupled to the second memory array via a first word line; and
a second word line driver circuit coupled to the fourth memory array via a second word line;
wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.
13 . The system of claim 12 , wherein, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL; and
wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.