Synchronized system-on-chip telemetry aggregation and buffering
Embodiments of the present disclosure include techniques for synchronized telemetry aggregation and buffering in a system-on-chip (SoC). A first set of telemetry data associated with operation of a plurality of processor cores of the SoC during a first epoch is received. A second set of telemetry data associated with operation of the plurality of processor cores during a second epoch is received. The first set of telemetry data is determined as corresponding to an incomplete set of telemetry data for the first epoch. A message is transmitted to one or more controllers of the plurality of processor cores to modify operations associated with telemetry data collection as a result of the determination.
1 . A method, comprising:
receiving a first set of telemetry data associated with operation of a plurality of processor cores of a System-on-Chip (SoC) during a first epoch for telemetry data collection;
receiving a second set of telemetry data associated with operation of the plurality of processor cores during a second epoch for telemetry data collection;
wherein the first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and wherein the method further comprising updating a first bit of a status register and a second bit of the status register in response to receiving the first set of telemetry data, the first bit corresponding to a first type of telemetry data and the second bit corresponding to a second type of telemetry data;
determining that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch; and
transmitting, as a result of determining that the first set of telemetry data corresponds to an incomplete set, a message to one or more controllers of the plurality of processor cores to modify operations associated with telemetry data collection.
2 . The method of claim 1 , wherein the defined condition is an epoch overlap condition in which the first epoch overlaps in part with a second epoch for telemetry data collection.
3 . The method of claim 1 , the method comprising:
receiving a third set of telemetry data associated with operation of the plurality of processor cores during a third epoch for telemetry data collection; and
determining that one or more telemetry data instances for the first epoch are missing at a time when the third set of telemetry data was received.
4 . The method of claim 1 , comprising:
storing the first set of telemetry data in a first section of a circular buffer;
storing the second set of telemetry data in a second section of the circular buffer;
updating a first status bit of a first plurality of status bits associated with the first epoch in a status register in connection with storing the first set of telemetry data in the first section; and
updating a second status bit of a second plurality of status bits associated with the second epoch in the status register in connection with storing the second set of telemetry data in the second section, wherein determining that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second plurality of status bits to a defined state.
5 . The method of claim 1 , comprising:
determining that the second set of telemetry data corresponds to a complete set of telemetry data for a second epoch for telemetry data collection, the second epoch different than the first epoch, wherein transmitting the message is in response to a determination that the second epoch is concluded before receiving a complete first set of telemetry data for the first epoch.
6 . The method of claim 1 , further comprising:
updating a third bit of the status register and a fourth bit of the status register in response to receiving the second set of telemetry data, the third bit corresponding to the first type of telemetry data and the fourth bit corresponding to the second type of telemetry data.
7 . The method of claim 1 , wherein the message includes instructions for modifying a state of a trigger signal, and wherein collection of telemetry data for one or more processor cores of the plurality of processor cores is enabled or disabled based on the state.
8 . A system comprising:
memory;
a telemetry memory bridge configured to:
receive a first set of telemetry data associated with operation of a plurality of processor cores of a System-on-Chip (SoC) during a first epoch for telemetry data collection;
receive a second set of telemetry data associated with operation of the plurality of processor cores during a second epoch for telemetry data collection;
store the first set of telemetry data and the second set of telemetry data in the memory;
determine that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch; and
generate an error status as a result of a determination that the first set of telemetry data corresponds to an incomplete set of telemetry data; and
one or more control processors configured to:
detect the error status; and
transmit, as a result of the error status detected, a message to one or more controllers of the plurality of processor cores to modify operations associated with telemetry data collection.
9 . The system of claim 8 , wherein the defined condition is an epoch overlap condition in which the first epoch overlaps in part with a second epoch for telemetry data collection.
10 . The system of claim 8 , the telemetry memory bridge configured to:
receive a third set of telemetry data associated with operation of the plurality of processor cores during a third epoch for telemetry data collection; and
determine that one or more telemetry data instances for the first epoch are missing at a time when the third set of telemetry data was received.
11 . The system of claim 8 , the telemetry memory bridge configured to:
store the first set of telemetry data in a first section of a circular buffer;
store the second set of telemetry data in a second section of the circular buffer;
update a first status bit of a first plurality of status bits associated with the first epoch in a status register in connection with storing the first set of telemetry data in the first section; and
update a second status bit of a second plurality of status bits associated with the second epoch in the status register in connection with storing the second set of telemetry data in the second section, wherein a determination that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second plurality of status bits to a defined state.
12 . The system of claim 8 , the telemetry memory bridge configured to:
determine that the second set of telemetry data corresponds to a complete set of telemetry data for a second epoch for telemetry data collection, the second epoch different than the first epoch, wherein transmitting the message is in response to a determination that the second epoch is concluded before the first epoch.
13 . The system of claim 8 , wherein the first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, the telemetry memory bridge configured to:
update a first bit of a status register and a second bit of the status register in response to receiving the first set of telemetry data, the first bit corresponding to the first type of telemetry data and the second bit corresponding to the second type of telemetry data; and
update a third bit of the status register and a fourth bit of the status register in response to receiving the second set of telemetry data, the third bit corresponding to the first type of telemetry data and the fourth bit corresponding to the second type of telemetry data.
14 . The system of claim 8 , wherein the message includes instructions for modifying a state of a trigger signal, and wherein collection of telemetry data for one or more processor cores of the plurality of processor cores is enabled or disabled based on the state.
15 . A system-on-chip, comprising:
a plurality of processor cores;
memory;
a telemetry memory bridge coupled to the memory;
a control processor communicatively coupled with the telemetry memory bridge; and
a plurality of mesh network routers each configured to route telemetry data associated with one or more of the processor cores toward the telemetry memory bridge, the telemetry memory bridge configured to:
receive a first set of telemetry data associated with operation of the plurality of processor cores during a first epoch for telemetry data collection, the first set of telemetry data transmitted by a mesh network router of the plurality of mesh network routers;
receive a second set of telemetry data associated with operation of the plurality of processor cores during a second epoch for telemetry data collection, the second set of telemetry data transmitted by a mesh network router;
store the first set of telemetry data and the second set of telemetry data in the memory;
determine that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch; and
generate an error status as a result of a determination that the first set of telemetry data corresponds to an incomplete set of telemetry data,
the control processor configured to:
detect the error status; and
transmit a message to one or more controllers of the plurality of processor cores to modify operations associated with telemetry data collection.
16 . The system-on-chip of claim 15 , the telemetry memory bridge including a status register having a first plurality of status bits associated with the first epoch and having a second plurality of status bits associated with the second epoch, the telemetry memory bridge configured to:
update a first status bit of the first plurality of status bits in response to receipt of the first set of telemetry data; and
update the second status bit of the second plurality of status bits in response to receipt of the second set of telemetry data, wherein the control processor determines that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second plurality of status bits to a defined state.
17 . The system-on-chip of claim 15 , the telemetry memory bridge including a mask register having a first mask bit associated with a first processor core of the plurality of processor cores and a second mask bit associated with a second processor core of the plurality of processor cores, the telemetry memory bridge configured to:
determine a first result associated with the first status bit based on a value of the first mask bit; and
determine a second result associated with the second status bit based on a value of the second mask bit, wherein a determination that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch is based on the first result or the second result.
18 . The system-on-chip of claim 15 , wherein the defined condition is an epoch overlap condition in which the first epoch overlaps in part with a second epoch for telemetry data collection.
19 . The system-on-chip of claim 15 , the telemetry memory bridge configured to:
receive a third set of telemetry data associated with operation of the plurality of processor cores during a third epoch for telemetry data collection; and
determine that one or more telemetry data instances for the first epoch are missing at a time when the third set of telemetry data was received.
20 . The system-on-chip of claim 15 , the telemetry memory bridge configured to:
determine that the second set of telemetry data corresponds to a complete set of telemetry data for a second epoch for telemetry data collection, the second epoch different than the first epoch, wherein transmitting the message is in response to a determination that the second epoch is concluded before the first epoch.