IP Library Granted Patent US 12,155,377
Granted Patent B2
US 12,155,377 · App. 17/836,114 · Granted Nov 26, 2024

Gate drive circuit of switching circuit including n-channel type transistor

Inventor: Hiroki Niikura (Kyoto, JP)
Assignee: ROHM CO., LTD.
H03K17/0822H02M1/0006H02M1/08H02M1/32H02M3/158H03K3/356113H03K19/018528H03K2217/0063H03K2217/0072
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Quick Facts
Patent No.
US 12,155,377
App. No.
17/836,114
Granted
Nov 26, 2024
Kind
B2
Abstract

A switching circuit includes a high-side transistor and a low-side transistor, each of which is of an N-channel type. A switch and a rectifying element of a PMOS transistor are provided in series between a constant voltage line through which a constant voltage is supplied and a bootstrap line. A comparison circuit operates using a high-side power supply voltage, which is a potential difference between the bootstrap line and a switching line, as a power supply to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage. A level shift circuit level-shifts the detection signal down to a signal of which a ground voltage is low. A PMOS driver drives the switch asynchronously with switching of the low-side transistor in response to an output of the level shift circuit.

Claims (27)

1. A gate drive circuit of a switching circuit including a high-side transistor and a low-side transistor, each of which is of an N-channel type, the gate drive circuit comprising:

a switching terminal to be coupled to a source of the high-side transistor, a drain of the low-side transistor, and one end of a bootstrap capacitor;

a bootstrap terminal to be coupled to another end of the bootstrap capacitor;

a switching line coupled to the switching terminal;

a bootstrap line coupled to the bootstrap terminal;

a high-side driver having an output to be coupled to a gate of the high-side transistor, having an upper power supply node coupled to the bootstrap line, and having a lower power supply node coupled to the switching line;

a low-side driver having an output to be coupled to a gate of the low-side transistor;

a switch and a rectifying element of a P-channel metal oxide semiconductor (PMOS) transistor provided in series between a constant voltage line to which a constant voltage is supplied and the bootstrap line;

a comparison circuit structured to operate using a high-side power supply voltage as a power supply, the high-side power supply voltage being a potential difference between the bootstrap line and the switching line, to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage;

a level shift circuit structured to level-shift the detection signal down to a signal of which a ground voltage is low; and

a PMOS driver structured to drive the switch asynchronously with switching of the high-side transistor in response to an output of the level shift circuit,

wherein the level shift circuit includes:

a pulse generator structured to generate a set pulse and a reset pulse having a predetermined pulse width in response to a positive edge and a negative edge of the detection signal, respectively;

a first open drain circuit including a first transistor having a source coupled to the bootstrap line and structured to turn on in response to the set pulse, and a second transistor having a source coupled to the bootstrap line and structured to turn on in response to the reset pulse;

a latch circuit including a third transistor and a fourth transistor that are cross-coupled, the latch circuit being structured to make a state transition in response to an output of the first open drain circuit;

a logic circuit structured to output a signal corresponding to a state of the latch circuit; and

an assist circuit structured to sink a first assist current from a drain of the fourth transistor in response to the set pulse, and to sink a second assist current from a drain of the third transistor in response to the reset pulse,

wherein the logic circuit includes:

a level shift and latch circuit structured to latch and level shift down an output of the latch circuit; and

two stage inverters structured to receive an output signal of the level shift and latch circuit,

and wherein the assist circuit includes:

a second open drain circuit including a fifth transistor having a source coupled to the bootstrap line and structured to turn on in response to the set pulse, and a sixth transistor having a source coupled to the bootstrap line and structured to turn on in response to the reset pulse; and

a first current mirror structured to fold a current through the fifth transistor so as to generate the first assist current; and

a second current mirror structured to fold a current through the sixth transistor so as to generate the second assist current.

2. The gate drive circuit according to claim 1 , wherein the level shift circuit further includes a latch stabilization circuit provided between a power supply line and a ground line and structured to fix, at a low level, one of complementary first node and second node of the latch circuit in accordance with the output of the level shift circuit.

3. A control circuit of a switching power supply, comprising the gate drive circuit according to claim 1 .

4. A switching power supply comprising the gate drive circuit according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2022
From: NIIKURA, HIROKI
To: ROHM CO., LTD.
Reel/Frame 060181/0768 →
Priority Claims (1)
JP 2019-224735 · Dec 12, 2019 · national
Continuity (2)
Continuation PCTJP2020046076 · Dec 10, 2020
Related Publication 20220321116A1 · Oct 6, 2022
Cited By (1)
US 12,525,979