IP Library Granted Patent US 11,715,509
Granted Patent B2
US 11,715,509 · App. 17/836,213 · Granted Aug 1, 2023

Semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Hajime Kimura (Atsugi, JP); Atsushi Miyaguchi (Hadano, JP); Yoshiaki Oikawa (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/405G06N3/04G06N3/063G06N3/08H01L29/7869H10B12/00
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Quick Facts
Patent No.
US 11,715,509
App. No.
17/836,213
Granted
Aug 1, 2023
Kind
B2
Abstract

A semiconductor device that enables lower power consumption and data storage imitating a human brain is provided. The semiconductor device includes a control unit, a memory unit, and a sensor unit. The memory unit includes a memory circuit and a switching circuit. The memory circuit includes a first transistor and a capacitor. The switching circuit includes a second transistor and a third transistor. The first transistor and the second transistor include a semiconductor layer including a channel formation region with an oxide semiconductor, and a back gate electrode. The control unit has a function of switching a signal supplied to the back gate electrode, in accordance with a signal obtained at the sensor unit.

Claims (31)

1. A semiconductor device comprising a control unit, a memory unit, and a sensor unit,

wherein the memory unit comprises a first memory circuit part, a second memory circuit part, and a switching circuit,

wherein the switching circuit is provided between the first memory circuit part and the second memory circuit part,

wherein the first memory circuit part comprises a first memory circuit and a second memory circuit,

wherein each of the first memory circuit and the second memory circuit is configured to change an information storage period in accordance with a signal obtained at the sensor unit,

wherein the first memory circuit comprises a first transistor,

wherein the switching circuit comprises a second transistor and a third transistor, and

wherein the control unit is configured to switch signals supplied to the first transistor and the second transistor, in accordance with the signal obtained at the sensor unit.

2. The semiconductor device according to claim 1 , wherein the switching circuit is configured to control amount of current flowing between the first memory circuit part and the second memory circuit part.

3. The semiconductor device according to claim 1 , wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a channel formation region with an oxide semiconductor, a gate electrode, and a back gate electrode.

4. The semiconductor device according to claim 1 , wherein the third transistor is a p-channel transistor.

5. The semiconductor device according to claim 1 , wherein the sensor unit comprises at least one of a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor.

6. The semiconductor device according to claim 1 , wherein the switching circuit is a programmable device being able to store configuration data.

7. A semiconductor device comprising a control unit, a memory unit, and a sensor unit,

wherein the memory unit comprises a first memory circuit part, a second memory circuit part, and a switching circuit,

wherein the switching circuit is provided between the first memory circuit part and the second memory circuit part,

wherein the first memory circuit part comprises a first memory circuit and a second memory circuit,

wherein each of the first memory circuit and the second memory circuit is configured to change an information storage period in accordance with a signal obtained at the sensor unit,

wherein the second memory circuit part comprises a third memory circuit and a fourth memory circuit,

wherein each of the third memory circuit and the fourth memory circuit is configured to change an information storage period in accordance with the signal obtained at the sensor unit,

wherein the first memory circuit comprises a first transistor,

wherein the switching circuit comprises a second transistor and a third transistor, and

wherein the control unit is configured to switch signals supplied to the first transistor and the second transistor, in accordance with the signal obtained at the sensor unit.

8. The semiconductor device according to claim 7 ,

wherein the third memory circuit comprises a fourth transistor, and

wherein the control unit is electrically connected to the fourth transistor.

9. The semiconductor device according to claim 7 , wherein the switching circuit is configured to control amount of current flowing between the first memory circuit part and the second memory circuit part.

10. The semiconductor device according to claim 7 , wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a channel formation region with an oxide semiconductor, a gate electrode, and a back gate electrode.

11. The semiconductor device according to claim 7 , wherein the third transistor is a p-channel transistor.

12. The semiconductor device according to claim 7 , wherein the sensor unit comprises at least one of a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor.

13. The semiconductor device according to claim 7 , wherein the switching circuit is a programmable device being able to store configuration data.

Priority Claims (2)
JP 2018-114810 · Jun 15, 2018 · national
JP 2018-114813 · Jun 15, 2018 · national
Continuity (2)
Continuation 16972693
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