IP Library › Granted Patent US 12,575,783
Granted Patent B2
US 12,575,783 · App. 17/837,503 · Granted Mar 17, 2026

Systems and methods for seizure detection

Inventors: Joseph S. Friedman (Dallas, TX); Mehrdad Nourani (Richardson, TX); Hina Dave (Dallas, TX); Alexander J. Edwards (Melissa, TX); Xuan Hu (Plano, TX); Abbas A. Zaki (Plano, TX); Noah C. Parker (Denton, TX); Jay H. Harvey (Southlake, TX); Taeyoon Kim (Richardson, TX)
Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
A61B5/4094A61B5/0006A61B5/7225A61N1/36064A61N1/36139
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,575,783
App. No.
17/837,503
Granted
Mar 17, 2026
Kind
B2
Abstract

Systems and methods to detect seizures using analog circuitry. One example method generally includes obtaining, at a seizure detection system, one or more electroencephalogram (EEG) signals, detecting a plurality of features associated with each of the one or more EEG signals, generating a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities, and generating a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features.

Claims (89)

1 . A method to detect seizures comprising:

obtaining, at a seizure detection system, one or more electroencephalogram (EEG) signals;

detecting a plurality of features associated with each of the one or more EEG signals;

generating a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities; and

generating, via feature evaluation circuitry, a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features, the feature evaluation circuitry including:

one or more p-channel metal-oxide semiconductor (PMOS) transistors coupled in series between a voltage rail and a common node, wherein a gate of the one or more PMOS transistors is configured to receive at least one of the plurality of bitstreams,

one or more n-channel metal-oxide semiconductor (NMOS) transistors coupled in series between the common node and a reference potential node, wherein a gate of the one or more NMOS transistors is configured to receive the at least one of the plurality of bitstreams, and

a latch comprising one or more inverters coupled between the common node and an output of the feature evaluation circuitry.

2 . The method of claim 1 , further comprising:

generating an analog signal for each feature of the plurality of features,

wherein,

the bitstream is generated based on the analog signal, and

the analog signal includes a voltage corresponding to the seizure probability.

3 . The method of claim 1 , wherein a quantity of bits, in a specific time period, of the bitstream having a specific logic state indicates the seizure probability.

4 . The method of claim 1 , wherein a probability that each bit of the bitstream has a specific logic state is equal to the seizure probability.

5 . The method of claim 1 , wherein the seizure detection output is generated via a Muller C-element circuit through stochastic computing.

6 . The method of claim 1 , further comprising:

generating a feature evaluation signal based on a comparison of the plurality of bitstreams,

wherein,

the seizure detection output is generated based on the feature evaluation signal.

7 . The method of claim 6 , wherein the generating of the feature evaluation signal includes:

setting the feature evaluation signal to a specific logic state when corresponding bits of the plurality of bitstreams have a same logic state; and

setting the feature evaluation signal to a previous logic state when the corresponding bits of the plurality of bitstreams having different logic states.

8 . The method of claim 6 , further comprising:

filtering the feature evaluation signal to yield a filtered feature evaluation signal,

wherein,

the seizure detection output is generated based on the filtered feature evaluation signal.

9 . The method of claim 1 , further comprising:

selecting, based on measurements associated with a patient, the plurality of features from candidate features; and

before implanting the seizure detection system for the patient, configuring the seizure detection system to use the plurality of features for seizure detection based on the selection.

10 . The method of claim 1 , further comprising:

performing measurements associated with the plurality of features,

wherein,

detecting the plurality of features comprises detecting whether each of the measurements meets a measurement threshold or is within a measurement range.

11 . The method of claim 10 , further comprising:

selecting, based on measurements associated with a patient, the measurement threshold or the measurement range associated with each of the plurality of features; and

before implanting the seizure detection system for the patient, configuring the seizure detection system to use the measurement threshold or the measurement range for detecting each of the plurality of features based on the selection.

12 . An apparatus to detect seizures comprising:

a feature detection circuit configured to detect a plurality of features associated with one or more electroencephalogram (EEG) signals;

a bitstream generator configured to generate a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities; and

feature evaluation circuitry configured to generate a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features, the feature evaluation circuitry including:

a set of p-channel metal-oxide semiconductor (PMOS) transistors coupled in series between a voltage rail and a common node, wherein a gate of each of the set of PMOS transistors are configured to receive a respective one of the plurality of bitstreams,

a set of n-channel metal-oxide semiconductor (NMOS) transistors coupled in series between the common node and a reference potential node, wherein a gate of each of the set of NMOS transistors are configured to receive the respective one of the plurality of bitstreams, and

a latch comprising a pair of inverters coupled between the common node and an output of the feature evaluation circuitry.

13 . The apparatus of claim 12 , further comprising:

an analog voltage generation circuit configured to generate an analog signal for each feature of the plurality of features,

wherein,

the bitstream is generated based on the analog signal, and

the analog signal includes a voltage corresponding to the seizure probability.

14 . The apparatus of claim 13 ,

wherein,

the bitstream generator is configured to receive the analog signal and generate the bitstream based on the analog signal,

a quantity of bits, in a specific time period, of the bitstream having a specific logic state indicates the seizure probability.

15 . The apparatus of claim 12 ,

wherein,

the feature evaluation circuitry comprises a Muller c-element circuit configured to generate a feature evaluation signal, and

the seizure detection output is generated based on the feature evaluation signal.

16 . The apparatus of claim 12 ,

wherein,

the feature evaluation circuitry is configured to generate a feature evaluation signal based on a comparison of the plurality of bitstreams, and

the seizure detection output is generated based on the feature evaluation signal.

17 . The apparatus of claim 16 , wherein the feature evaluation circuitry is configured to generate the feature evaluation signal by:

setting the feature evaluation signal to a specific logic state when corresponding bits of the plurality of bitstreams have a same logic state; and

setting the feature evaluation signal to a previous logic state when the corresponding bits of the plurality of bitstreams having different logic states.

18 . The apparatus of claim 16 ,

wherein,

the feature evaluation circuitry includes a low-pass filter configured to filter the feature evaluation signal and yield a filtered feature evaluation signal, and

the seizure detection output is generated based on the filtered feature evaluation signal.

19 . The apparatus of claim 12 ,

wherein,

the feature detection circuit is configured to perform measurements associated with each of the plurality of features, and

to detect the plurality of features, the feature detection circuit is configured to detect whether each of the measurements meets a measurement threshold or is within a measurement range.

20 . The apparatus of claim 12 , further comprising:

a signal generator configured to:

generate an electrical stimulation signal in response to the seizure detection output; and

apply the electrical stimulation signal to a patient.

21 . The apparatus of claim 20 , further comprising:

a wireless receiver coupled to the signal generator and configured to receive a wireless signal from a wireless transmitter,

wherein,

the signal generator is configured to tune the electrical stimulation signal based on the wireless signal.

22 . A seizure detection system comprising:

one or more electrodes configured to generate one or more electroencephalogram (EEG) signals;

an amplification circuit configured to amplify the one or more EEG signals to yield one or more amplified EEG signals;

a feature detection circuit configured to detect a plurality of features associated with each of the one or more amplified EEG signals;

a bitstream generator configured to generate a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities; and

feature evaluation circuitry configured to generate a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features, the feature evaluation circuitry including:

one or more p-channel metal-oxide semiconductor (PMOS) transistors coupled in series between a voltage rail and a common node, wherein a gate of the one or more PMOS transistors is configured to receive at least one of the plurality of bitstreams,

one or more n-channel metal-oxide semiconductor (NMOS) transistors coupled in series between the common node and a reference potential node, wherein a gate of the one or more NMOS transistors is configured to receive the at least one of the plurality of bitstreams, and

a latch comprising one or more inverters coupled between the common node and an output of the feature evaluation circuitry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2022
From: FRIEDMAN, JOSEPH S.; NOURANI, MEHRDAD; DAVE, HINA; EDWARDS, ALEXANDER J.; HU, XUAN; ZAKI, ABBAS A.; PARKER, NOAH C.; HARVEY, JAY H.; KIM, TAEYOON
To: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
Reel/Frame 060725/0010 →
Continuity (2)
Provisional Application 63209837 · Jun 11, 2021
Related Publication 20220395217A1 · Dec 15, 2022
References Cited (41)
US 8641646B2 · Colborn · 2014 [cited by examiner]
US 10743809B1 · Kamousi · 2020 [cited by examiner]
US 20060111644A1 · Guttag · 2006 [cited by examiner]
US 20100121215A1 · Giftakis · 2010 [cited by examiner]
US 20110054583A1 · Litt · 2011 [cited by examiner]
US 20110230730A1 · Quigg · 2011 [cited by examiner]
US 20140121554A1 · Sarma · 2014 [cited by examiner]
US 20190059803A1 · Myers · 2019 [cited by examiner]
US 20190150774A1 · Brinkmann · 2019 [cited by examiner]
US 20190175028A1 · Osorio · 2019 [cited by examiner]
US 20230270345A1 · Osorio · 2023 [cited by examiner]
Zaki, AA, et al. “Analog Seizure Detection for Implanted Responsive Neurostimulation.” arXiv preprint arXiv:2106.06590 (2021). [cited by applicant]
World Health Orginization. (Jun. 2019) Epilepsy. [Online]. Available: https://www.who.int/news-room/fact-sheets/detail/epilepsy. [cited by applicant]
Boon P, et al. “Neurostimulation for drug-resistant epilepsy: a systematic review of clinical evidence for efficacy, safety, contraindications and predictors for response.” Current opinion in neurology 31.2 (2018): 198-… [cited by applicant]
Assi EB, et al. “Towards accurate prediction of epileptic seizures: A review.” Biomedical Signal Processing and Control 34 (2017): 144-157. [cited by applicant]
Davis P, et al. “Neuromodulation for the treatment of epilepsy: a review of current approaches and future directions.” Clinical Therapeutics 42.7 (2020): 1140-1154. [cited by applicant]
Alomar SA, et al. “Different modalities of invasive neurostimulation for epilepsy.” Neurological Sciences 41.12 (2020): 3527-3536. [cited by applicant]
Friedman JS, et al. “Bayesian inference with muller c-elements.” IEEE Transactions on Circuits and Systems I: Regular Papers 63.6 (2016): 895-904. [cited by applicant]
NeuroPace. (Jun. 2020) RNS system physician manual. [Online]. Available: https://www.neuropace.com/wp-content/uploads/2021/02/neuropace-rns-system-manual-320.pdf. [cited by applicant]
Chen WM, et al. “A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control.” IEEE journal of solid-state circuits 49.1 (2013): 232-247. [cited by applicant]
Pinto MF, et al. “A personalized and evolutionary algorithm for interpretable EEG epilepsy seizure prediction.” Scientific reports 11.1 (2021): 3415. [cited by applicant]
Yoo J, et al. “An 8-channel scalable EEG acquisition SoC with patient-specific seizure classification and recording processor.” IEEE journal of solid-state circuits 48.1 (2012): 214-228. [cited by applicant]
Altaf MA, et al. “A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator.” IEEE Journal of Solid-State Circuits 50.11 (2015): 2728-2740. [cited by applicant]
Gaines BR, Stochastic Computing Systems. Boston, MA: Springer US, 1969, pp. 37-172. [cited by applicant]
Hoe, DHK “Bayesian inference using stochastic logic: A study of buffering schemes for mitigating autocorrelation.” International Journal of Approximate Reasoning 112 (2019): 4-21. [cited by applicant]
Zhou S, et al. “An ultra-low power CMOS random number generator.” Solid-State Electronics 52.2 (2008): 233-238. [cited by applicant]
Yang K, et al. “A robust −40 to 120° C. all-digital true random number generator in 40nm CMOS.” 2015 Symposium on VLSI Circuits (VLSI Circuits). IEEE, 2015. [cited by applicant]
Mathew SK, et al. “μ Rng: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.” IEEE Journal of Solid-State Circuits 51.7 (2016): 1695-1704. [cited by applicant]
Vodenicarevic D, et al. “Low-energy truly random number generation with superparamagnetic tunnel junctions for unconventional computing.” Physical Review Applied 8.5 (2017): 054045. [cited by applicant]
Camsari KY, et al. “Stochastic p-bits for invertible logic.” Physical Review X 7.3 (2017): 031014. [cited by applicant]
Camsari KY, et al. “Implementing p-bits with embedded MTJ.” IEEE Electron Device Letters 38.12 (2017): 1767-1770. [cited by applicant]
Shah V, et al. “The temple university hospital seizure detection corpus.” Frontiers in neuroinformatics 12 (2018): 83. [cited by applicant]
Shoaran M, et al. “Energy-efficient classification for resource-constrained biomedical applications.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8.4 (2018): 693-707. [cited by applicant]
Truong ND, et al. “Convolutional neural networks for seizure prediction using intracranial and scalp electroencephalogram.” Neural Networks 105 (2018): 104-111. [cited by applicant]
Daoud H, et al. “Efficient epileptic seizure prediction based on deep learning.” IEEE transactions on biomedical circuits and systems 13.5 (2019): 804-813. [cited by applicant]
Yang J, et al. “From seizure detection to smart and fully embedded seizure prediction engine: A review.” IEEE Transactions on Biomedical Circuits and Systems 14.5 (2020): 1008-1023. [cited by applicant]
Muller R, et al. “A 0.013 mm2 , 5 μW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply,” in IEEE Journal of Solid-State Circuits, vol. 47, No. 1, pp. 232-243 (2012). [cited by applicant]
Xu X, et al. “A 1-V 450-nW fully integrated biomedical sensor interface system.” 2008 IEEE Symposium on VLSI Circuits. IEEE, 2008. [cited by applicant]
Zou X, et al. “A 1V 22μW 32-channel implantable EEG recording IC.” 2010 IEEE International Solid-State Circuits Conference—(ISSCC). IEEE, 2010. [cited by applicant]
Denison T, et al. “A 2.2/spl mu/W 94nV//spl radic/Hz, chopper-stabilized instrumentation amplifier for EEG detection in chronic implants.” 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Pap… [cited by applicant]
Sun FT, et al. “The RNS System: responsive cortical stimulation for the treatment of refractory partial epilepsy.” Expert review of medical devices 11.6 (2014): 563-572. [cited by applicant]