Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
1. A method comprising:
generating, using a phase interpolation control signal generator, a plurality of multi-bit control signals associated with a phase offset between a reference clock signal and a plurality of phases of a local oscillator signal, each multi-bit control signal comprising a set of branch-specific weights and associated with a corresponding phase of the local oscillator signal;
receiving, at two or more dynamically-weighted exclusive OR (XOR) phase comparators, the reference clock signal, different phases of the local oscillator signal and the multi-bit control signal associated with the received phase of the local oscillator;
generating, for each dynamically-weighted XOR phase comparator, a respective phase-error signal as a sequence of individually weighted segments, each individually weighted segment (i) generated responsive to a unique logical input combination of the reference clock signal and the received phase of the local oscillator signal and (ii) having a branch-specific weight from the set of branch specific weights of the received multi-bit control signal; and
generating an aggregate control signal for adjusting the plurality of phases of the local oscillator signal relative to the reference clock signal, the aggregate control signal corresponding to an analog summation of each respective phase-error signal.
2. The method of claim 1 , wherein generating each individually weighted segment comprises enabling one or more branch segments in parallel via bits associated with the branch-specific in the received multi-bit control signal.
3. The method of claim 2 , wherein each branch segment is enabled via series-connected transistors receiving the reference clock signal and the received phase of the local oscillator signal at inverting and non-inverting inputs determined by the unique logical input combination.
4. The method of claim 3 , wherein the series-connected transistors in each branch segment have equal dimensions, and the received multi-bit control signal comprises a thermometer-coded set of bits for each branch-specific weight.
5. The method of claim 3 , wherein the series-connected transistors in each branch segment have different dimensions, and the received multi-bit control signal comprises a binary-coded set of bits for each branch-specific weight.
6. The method of claim 1 , wherein at least two individually weighted segments of the sequence of individually weighted segments have different magnitudes and different durations.
7. The method of claim 1 , wherein the plurality of phases of the local oscillator comprises at least four phases.
8. The method of claim 1 , wherein the different phases of the local oscillator are adjacent phases.
9. The method of claim 1 , wherein the sets of branch-specific weights for the different phases of the local oscillator signal are inverses of each other.
10. The method of claim 1 , further comprising filtering the aggregate control signal using a low-pass filter.
11. An apparatus comprising:
a local oscillator configured to generate a plurality of phases of a local oscillator signal;
a phase interpolation (PI) control signal generator configured to generate a plurality of multi-bit control signals associated with a phase offset between a reference clock signal and the local oscillator signal, each multi-bit control signal comprising a set of branch-specific weights and associated with a corresponding phase of the local oscillator signal;
at least two dynamically-weighted exclusive OR (XOR) phase comparators configured to receive the reference clock signal, different phases of the local oscillator signal and the multi-bit control signal associated with the received phase of the local oscillator, each dynamically-weighted XOR phase comparator configured to generate a respective phase-error signal as a sequence of individually weighted segments, each individually weighted segment (i) generated responsive to a unique logical input combination of the reference clock signal and the received phase of the local oscillator signal and (ii) having a branch-specific weight from the set of branch specific weights of the received multi-bit control signal; and
a common output node connected to the at least two dynamically-weighted XOR phase comparators, the common output node configured to receive each respective phase-error signal and to generate an aggregate control signal for adjusting the plurality of phases of the local oscillator signal relative to the reference clock signal.
12. The apparatus of claim 11 , wherein each branch-specific weight corresponds to a plurality of branch segments enabled in parallel via bits associated with the branch-specific in the received multi-bit control signal.
13. The apparatus of claim 12 , wherein each branch segment comprises series-connected transistors receiving the reference clock signal and the received phase of the local oscillator signal at inverting and non-inverting inputs determined by the unique logical input combination.
14. The apparatus of claim 13 , wherein the series-connected transistors in each branch segment have equal dimensions, and the received multi-bit control signal comprises a thermometer-coded set of bits for each branch-specific weight.
15. The apparatus of claim 13 , wherein the series-connected transistors in each branch segment have different dimensions, and the received multi-bit control signal comprises a binary-coded set of bits for each branch-specific weight.
16. The apparatus of claim 11 , wherein at least two individually weighted segments of the sequence of individually weighted segments have different magnitudes and different durations.
17. The apparatus of claim 11 , wherein the plurality of phases of the local oscillator comprises at least four phases.
18. The apparatus of claim 11 , wherein the different phases of the local oscillator are adjacent phases.
19. The apparatus of claim 11 , wherein the sets of branch-specific weights for the different phases of the local oscillator signal are inverses of each other.
20. The apparatus of claim 11 , further comprising a low-pass filter connected between the common output node and the local oscillator, the low-pass filter configured to filter the aggregate control signal.