FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS

1 . An apparatus comprising:

a circuit board;

an active interposer coupled with the circuit board via a debug package;

a graphics processor die coupled with the active interposer via the debug package, wherein the graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device; and

a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality of a die of the multi-die SoC device to enable validation of the graphics processor die.

2 . The apparatus as in claim 1 , wherein the active interposer includes a connector to the graphics processor die that is controlled by the FPGA.

3 . The apparatus as in claim 2 , wherein the connector to the graphics processor die is controlled by the FPGA via general-purpose input/output (GPIO) connectors of the FPGA.

4 . The apparatus as in claim 1 , wherein the active interposer includes first power rails to power the graphics processor die.

5 . The apparatus as in claim 4 , wherein the active interposer includes digital logic and second power rails to power the digital logic.

6 . The apparatus as in claim 5 , wherein the digital logic includes base die digital logic associated with the multi-die SoC device.

7 . The apparatus as in claim 1 , wherein the FPGA includes:

a first die including first configurable logic blocks, the first configurable logic blocks configurable to include a first shim, the first shim coupled with an on-chip fabric of the graphics processor die via the active interposer; and

a second die including second configurable logic blocks, the second configurable logic blocks configurable to die programmable to include a second shim, the second shim coupled with a compute express link (CXL) interconnect of the graphics processor die via the active interposer.

8 . The apparatus as in claim 7 , wherein the first configurable logic blocks are configurable to include circuitry to interconnect the on-chip fabric to first CXL circuitry of the second die.

9 . The apparatus as in claim 8 , wherein the first configurable logic blocks are configurable to include a power management circuit configured to perform power management for the graphics processor die.

10 . The apparatus as in claim 9 , wherein the second configurable logic blocks are configurable to include second CXL circuitry, the second CXL circuitry to couple the first shim to a peripheral component interconnect express (PCIe) packetizer.

11 . A method comprising:

establishing communication with a graphics compute die (GCD) associated with a chiplet for a multi-die system on chip (SoC) device, the communication established via a field-programmable gate array (FPGA), the FPGA including hardware logic that is configurable to emulate functionality of a die of the multi-die SoC device;

receiving signals at the FPGA via a system interconnect and, in response to the signals, driving interconnects to the GCD via general-purpose input/output (GPIO) to cause the GCD to boot into an operational state; and

emulating functionality of the die of the multi-die SoC device to facilitate execution of a silicon validation test on the GCD.

12 . The method as in claim 11 , further comprising receiving signals via the system interconnect based a set of debugger commands issued by a host data processing system in communication with the FPGA via the system interconnect.

13 . The method as in claim 12 , further comprising:

gathering data on signals within the FPGA via data collectors within the FPGA during execution of the silicon validation test on the GCD; and

exporting the data to the host data processing system via the system interconnect.

14 . The method as in claim 13 , further comprising gathering data on signals associated with compute express link (CXL) circuitry implemented via the FPGA.

15 . The method as in claim 13 , further comprising gathering data on signals associated with power management circuitry implemented via the FPGA.

16 . The method as in claim 11 , further comprising establishing a connection between the GCD and a debug host via a debug interface and monitoring state information of the GCD during execution of the silicon validation test.

17 . A system comprising:

a system interface; and

a circuit board including:

an active interposer coupled with the circuit board via a debug package;

a graphics processor die coupled with the active interposer via the debug package, wherein the graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device; and

a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate system interface and power management circuitry of a system die of the multi-die SoC device, the FPGA to enable validation of the graphics processor die separately from the system die.

18 . The system as in claim 17 , wherein the active interposer includes a connector to the graphics processor die that is controlled by the FPGA.

19 . The system as in claim 17 , wherein the system interface is a peripheral component interconnect express (PCIe) interface configured to couple with a host data processing system and the system interface is configured to couple with system interface circuitry implemented via the FPGA.

20 . The system as in claim 19 , wherein the system interface circuitry implemented via the FPGA includes compute express link (CXL) circuitry.