Granted Patent B2

US 12,426,857 · App. 17/841,257 · Granted Sep 30, 2025

Inventors: Jonathan M. Rothberg (Miami Beach, FL); Tyler S. Ralston (Clinton, CT); Nevada J. Sanchez (Guilford, CT); Andrew J. Casper (Clinton, CT)

Assignee: BFLY Operations, Inc.

A61B8/56A61B8/4483A61B8/4494A61B8/488A61B8/5207G01S7/52033G01S7/52034G01S7/5208G01S7/52085G01S15/8915

Abstract

Claims (32)

1. An ultrasound device, comprising:

a semiconductor die;

an ultrasonic transducer array comprising at least 5,000 ultrasonic transducers integrated on the semiconductor die;

an analog receive circuit integrated on the semiconductor die, the analog receive circuit arranged to receive output signals from the ultrasonic transducer array;

an on-chip Hadamard encoding circuit integrated on the semiconductor die and connected to an output of the analog receive circuit, the on-chip Hadamard encoding circuit configured to generate a Hadamard encoded analog signal prior to any image reconstruction process being performed by applying a Hadamard encoding for at least some ultrasonic transducers in the ultrasonic transducer;

an analog to digital converter (ADC) integrated on the semiconductor die and configured to produce a digital signal based on the Hadamard encoded analog signal; and

a digital signal processing block configured to perform at least a portion of an image reconstruction process based on the digital signal.

2. The ultrasound device of claim 1 , further comprising:

a digital compression circuit integrated on the semiconductor die and configured to generate a compressed digital signal by compressing the digital signal to be transmitted from the semiconductor die as a data stream to the digital signal processing block, and wherein the digital signal processing block is configured to perform at least a portion of an image reconstruction process based on the compressed digital signal.

3. The ultrasound device of claim 2 , wherein the digital compression circuit is configured to perform one or more of: quadrature demodulation, downsampling, quadrature sampling, filtered downsampling, cascade integrating comb (CIC) filtering, receive aperture filtering, polyphase filtering, re-quantization, and pulse compression.

4. The ultrasound device of claim 1 , further comprising image reconstruction circuitry configured to perform at least a portion of the image reconstruction process, wherein

the image reconstruction circuitry is configured to perform at least a portion of an image reconstruction process using a beamforming technique.

5. The ultrasound device of claim 4 , wherein the beamforming technique comprises an integrated backprojection technique, in which at least one of receiver time-of-flight values and receive apodization values are reused within consecutive scans.

6. The ultrasound device of claim 1 , wherein the ADC comprises one more of: a successive approximation register (SAR) ADC, a flash ADC, a pipeline ADC, a sigma-delta ADC, a multi-slop ADC, and a time-interleaved ADC.

7. The ultrasound device of claim 1 , wherein the ADC comprises a 10-bit ADC configured to operate at a conversion rate selected from the group consisting of: 20 mega-samples per second (Msps), 40 Msps, 50 Msps, and 80 Msps.

8. A method for processing output signals from a transducer array comprising at least 5,000 ultrasonic transducers integrated on a semiconductor die, the method comprising:

with an analog receive circuit integrated on the semiconductor die, receiving output signals from the transducer array;

with an on-chip Hadamard encoding circuit integrated on the semiconductor die,

receiving an output of the analog receive circuit, and

based on the received output, generating a Hadamard encoded analog signal prior to any image reconstruction process being performed by applying a Hadamard encoding for at least some ultrasonic transducers in the transducer array; and

with an analog to digital converter (ADC) integrated on the semiconductor die, producing a digital signal based on the Hadamard encoded analog signal;

with a digital signal processing block, performing at least a portion of an image reconstruction process based on the digital signal.

9. The method of claim 8 , further comprising:

with a digital compression circuit integrated on the semiconductor die, generating a compressed digital signal by compressing the digital signal, and the method further comprises:

transmitting the compressed digital signal from the semiconductor die as a data stream to the digital signal processing block, wherein

the act of performing at least a portion of an image reconstruction process is based on the compressed digital signal.

10. The method of claim 9 , wherein generating the compressed digital signal comprises performing one or more of: quadrature demodulation, downsampling, quadrature sampling, filtered downsampling, cascade integrating comb (CIC) filtering, receive aperture filtering, polyphase filtering, re-quantization, and pulse compression.

11. The method of claim 8 , wherein performing at least a portion of an image reconstruction process further comprises

with an image reconstruction circuitry, performing at least a portion of the image reconstruction process using a beamforming technique.

12. The method of claim 11 , wherein using the beamforming technique comprises using an integrated backprojection technique, in which at least one of receiver time-of-flight values and receive apodization values are reused within consecutive scans.

13. The method of claim 8 , wherein the ADC comprises one more of: a successive approximation register (SAR) ADC, a flash ADC, a pipeline ADC, a sigma-delta ADC, a multi-slop ADC, and a time-interleaved ADC.

14. The method of claim 8 , wherein producing a digital signal with the ADC comprises operating a 10-bit ADC at a conversion rate selected from the group consisting of: 20 mega-samples per second (Msps), 40 Msps, 50 Msps, and 80 Msps.

Assignments (2)

Continuity (4)

References Cited (302)