IP Library Granted Patent US 12,614,903
Granted Patent B2
US 12,614,903 · App. 17/842,172 · Granted Apr 28, 2026

External usb-c hardware failure protection

Inventor: Shailendra Singh Chauhan (Bengaluru, IN)
Assignee: Intel Corporation
H02H3/16H02H1/0007
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Quick Facts
Patent No.
US 12,614,903
App. No.
17/842,172
Granted
Apr 28, 2026
Kind
B2
Abstract

USB ports such as Type-C USB-C ports in a personal computer (PC) or other computing device may be configured in dual-role port (DRP) mode. The DRP mode may provide the ability for a port to switch between providing power to an external device and receiving power from an external power source to the into the computing device. The voltage level received from an external power source is typically higher than the voltage level provided to an external device. When a USB device fails, it may apply the higher voltage level to an external device, which may cause the external device to fail. A voltage sense and device detection circuit which may be used to detect an internal failure and prevent a higher internal voltage to be applied to a USB device.

Claims (43)

1 . A system comprising:

a power delivery controller (PD) circuit configured to switchably couple a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port;

a transistor group configured to switchably couple a second voltage conductor to the VBUS conductor;

a voltage sense circuit to:

detect a short circuit between the first voltage conductor and the VBUS conductor; and

reduce a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit; and

a pull-down transistor configured to switchably couple the transistor group to a ground, wherein reducing the short circuit voltage includes causing the pull-down transistor to couple the transistor group to the ground.

2 . The system of claim 1 , further including a fuse coupled between the transistor group and the pull-down transistor;

wherein coupling the transistor group to the ground causes an open circuit at the fuse.

3 . The system of claim 2 , wherein:

the fuse includes a slow-blow fuse; and

a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.

4 . The system of claim 1 , wherein the detection of the short circuit includes:

determining no USB device is connected to the USB port; and

determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.

5 . The system of claim 4 , further including a configuration channel conductor on the USB port;

wherein determining that no USB device is connected to the USB port is based on a configuration indication received from the configuration channel conductor at the voltage sense circuit.

6 . The system of claim 1 , further including a system-on-a-chip (SOC) to receive an indication of the detection of the short circuit from the voltage sense circuit.

7 . A method comprising:

detecting a short circuit at a transistor group conductively coupled between a first voltage conductor and a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port, the short circuit detected at a voltage sense circuit; and

reducing a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit,

wherein reducing the short circuit voltage includes causing a pull-down transistor to couple the transistor group to a ground.

8 . The method of claim 7 , wherein coupling the transistor group to the ground includes causing an open circuit at a fuse coupled between the transistor group and the pull-down transistor.

9 . The method of claim 8 , wherein:

the fuse includes a slow-blow fuse; and

a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.

10 . The method of claim 7 , further including receiving an indication of the detection of the short circuit at a system-on-a-chip (SOC) from the voltage sense circuit.

11 . The method of claim 7 , wherein the detection of the short circuit includes:

determining no USB device is connected to the USB port; and

determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.

12 . The method of claim 11 , wherein determining that no USB device is connected to the USB port is based on a configuration indication received from a configuration channel conductor at the voltage sense circuit.

13 . At least one non-transitory machine-readable storage medium, comprising a plurality of instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the processor circuitry to:

detect a short circuit at a transistor group conductively coupled between a first voltage conductor and a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port, the short circuit detected at a voltage sense circuit; and

reduce a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit, wherein reducing the short circuit voltage includes causing a pull-down transistor to couple the transistor group to a ground.

14 . The at least one non-transitory machine-readable storage medium of claim 13 , wherein coupling the transistor group to the ground includes causing an open circuit at a fuse coupled between the transistor group and the pull-down transistor.

15 . The at least one non-transitory machine-readable storage medium of claim 14 , wherein:

the fuse includes a slow-blow fuse; and

a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.

16 . The at least one non-transitory machine-readable storage medium of claim 13 , the instructions further causing the processor circuitry to receive an indication of the detection of the short circuit at a system-on-a-chip (SOC) from the voltage sense circuit.

17 . The at least one non-transitory machine-readable storage medium of claim 13 , wherein the detection of the short circuit includes:

determining no USB device is connected to the USB port; and

determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.

18 . The at least one non-transitory machine-readable storage medium of claim 17 , wherein determining that no USB device is connected to the USB port is based on a configuration indication received from a configuration channel conductor at the voltage sense circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2022
From: CHAUHAN, SHAILENDRA SINGH
To: INTEL CORPORATION
Reel/Frame 060666/0768 →
Continuity (1)
Related Publication 20230411950A1 · Dec 21, 2023
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