Granted Patent B2

US 12,563,989 · App. 17/842,627 · Granted Feb 24, 2026

Inventors: Georgios Vellianitis (Heverlee, BE); Oreste Madia (Brussels, BE); Gerben Doornbos (Kessel-Lo, BE); Marcus Johannes Henricus Van Dal (Linden, BE)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H01L21/3086H01L21/02112H01L21/30604H10D30/6735H10D64/252H01L21/76897H10D30/62H10D64/017H10D64/2523

Abstract

Claims (46)

1 . A method, comprising:

forming first sacrificial layers and first channel layers alternately stacked over a substrate;

forming a dielectric isolation layer over the first sacrificial layers and the first channel layers, wherein the dielectric isolation layer is in contact with a topmost one of the first channel layers;

after forming the dielectric isolation layer, forming second channel layers and second sacrificial layers alternately stacked over the dielectric isolation layer, wherein the second channel layers are made of a first semiconductive oxide, and wherein the dielectric isolation layer is in contact with a bottommost one of the second channel layers;

performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers;

forming a gate structure in contact with the first channel layers and the second channel layers;

forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and

forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

2 . The method of claim 1 , wherein the first channel layers are made of a semiconductor material.

3 . The method of claim 1 , wherein the first channel layers are made of a second semiconductive oxide different from the first semiconductive oxide.

4 . The method of claim 3 , wherein the first semiconductive oxide comprises IGZO, IZO, InO x , GaO x , and the second semiconductive oxide comprises tin oxide, copper oxide, nickel oxide.

5 . The method of claim 1 , wherein the gate structure is in contact with the dielectric isolation layer.

6 . The method of claim 1 , further comprising performing a selective epitaxial growth to forming source/drain epitaxy structures in contact with the first channel layers and on the opposite sides of the gate structure, wherein the source/drain epitaxy structures are not formed on the second channel layers.

7 . A method, comprising:

forming first sacrificial layers and first channel layers alternately stacked over a substrate;

forming an isolation layer in contact with a topmost one of the first channel layers;

after forming the isolation layer, forming second channel layers and second sacrificial layers alternately stacked over the isolation layer, wherein a bottommost one of the second channel layers is in contact with the isolation layer;

performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers;

forming a gate structure in contact with the first channel layers and the second channel layers;

forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers;

forming a dielectric layer over the first source/drain contacts; and

after forming the dielectric layer, forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

8 . The method of claim 7 , wherein the first and second channel layers are made of different semiconductive oxides.

9 . The method of claim 8 , wherein the first and second sacrificial layers are made of a dielectric material.

10 . The method of claim 7 , wherein the first channel layers are made of semiconductor material, and the second channel layers are made of semiconductive oxide.

11 . The method of claim 7 , further comprising forming source/drain epitaxy structures on the opposite sides of the gate structure, wherein the source/drain epitaxy structures are in contact with the first channel layers, and the second source/drain contacts are in contact with the second channel layers.

12 . The method of claim 7 , wherein the isolation layer is thicker than the first channel layers and the second channel layers.

13 . A semiconductor device, comprising:

a substrate;

a first transistor over the substrate, wherein the first transistor comprises:

first channel layers stacked over the substrate;

a first gate structure over the first channel layers; and

first source/drain contacts on opposite sides of the first gate structure; and

a second transistor over the first transistor, wherein the second transistor comprises:

second channel layers stacked over the first channel layers, wherein the second channel layers are made of a semiconductive oxide;

a second gate structure over the first channel layers and the second channel layers;

second source/drain contacts on opposite sides of the second gate structure, wherein the first and second source/drain contacts are made of metal, and wherein the second source/drain contacts wrap around and interface with the second channel layers; and

a dielectric layer between one of the first source/drain contacts and one of the second source/drain contacts, wherein a bottom surface of the dielectric layer is in contact with the one of the first source/drain contacts; and

an isolation layer vertically between the first channel layers and the second channel layers, wherein the isolation layer extends from a first position vertically between the first gate structure and the second gate structure to a second position vertically between the one of the first source/drain contacts and the one of the second source/drain contacts.

14 . The semiconductor device of claim 13 , wherein the second channel layers comprise IGZO, IZO, InO x , GaO x .

15 . The semiconductor device of claim 13 , wherein the first channel layers are made of a semiconductor material.

16 . The semiconductor device of claim 13 , wherein the isolation layer is in contact with a topmost one of the first channel layers and a bottommost one of the second channel layers.

17 . The semiconductor device of claim 13 , wherein the first transistor further comprises source/drain epitaxy structures on the opposite sides of the first gate structure and in contact with the first channel layers.

18 . The semiconductor device of claim 13 , wherein the isolation layer is in contact with a sidewall of the dielectric layer.

19 . The semiconductor device of claim 13 , further comprising a via extending through the dielectric layer to the one of the first source/drain contacts.

20 . The semiconductor device of claim 19 , wherein the via is laterally spaced apart from the one of the second source/drain contacts through a dielectric material.

Assignments (1)

Continuity (1)

References Cited (23)