Memory cell layout for low current field-induced MRAM
Provided herein is a cell of a magnetic random access memory (MRAM) circuit. The cell includes a horizontal outer perimeter and an access transistor including a first terminal, a second terminal, and a gate terminal. The cell includes a magnetic tunnel junction (MTJ) structure located in the horizontal outer perimeter and above the bottom electrode. The MTJ structure being centered within the horizontal outer perimeter. The cell includes a bottom electrode located entirely within the horizontal outer perimeter. The bottom electrode comprising a shape enabling the MTJ structure to be centered within the horizontal outer perimeter.
1. A cell of a magnetic random access memory (MRAM) circuit comprising:
a horizontal outer perimeter;
an access transistor including a first terminal, a second terminal, and a gate terminal;
a magnetic tunnel junction (MTJ) structure located in the horizontal outer perimeter and above electrode, the MTJ structure being centered within the horizontal outer perimeter; and
a bottom electrode located entirely within the horizontal outer perimeter, the bottom electrode configured as a seed layer for the MTJ structure that connects the MTJ structure to a via and comprising a shape enabling the MTJ structure to be centered within the horizontal outer perimeter,
wherein the cell is configured at a distance equal to a length of the horizontal outer perimeter from one or more neighboring cells of the MRAM circuit to minimize magnetic interactions between and to reduce variation in switching fields of the MJT structure of the cell and MJT structures of the one or more neighboring cells of the MRAM circuit.
2. The cell of the MRAM circuit of claim 1 , wherein the MTJ structure being centered within the horizontal outer perimeter reduces a variation in a switching field of the MTJ structure.
3. The cell of the MRAM circuit of claim 1 , wherein a size of the MTJ when the MRAM circuit is fabricated is equal to or greater than 45 nm by 45 nm.
4. The cell of the MRAM circuit of claim 1 , wherein the shape of the bottom electrode comprises a length spanning from a location of an interface via to a horizontal plane center.
5. The cell of the MRAM circuit of claim 4 , wherein the location of the interface via being closer to the horizontal outer perimeter than to the horizontal plane center.
6. The cell of the MRAM circuit of claim 1 , wherein a size of the MRAM circuit comprises the horizontal outer perimeter being equal to or greater than 180 nm by 140 nm.
7. The cell of the MRAM circuit of claim 1 , wherein a size of the MRAM circuit comprises the horizontal outer perimeter being a length to width ratio equal to or greater than 0.6.
8. The cell of the MRAM circuit of claim 1 , wherein a ratio of a length of the bottom electrode along an axis to a length of the MTJ structure along the same axis is equal to or greater than 1.9.
9. The cell of the MRAM circuit of claim 8 , wherein the ratio is 2.1 when the MRAM circuit is fabricated at a 32 nm complementary metal-oxide semiconductor (CMOS) process technology.
10. The cell of the MRAM circuit of claim 8 , wherein the ratio is 1.9 when the MRAM circuit is fabricated at a 45 nm CMOS process technology.
11. The cell of the MRAM circuit of claim 8 , wherein the ratio is 2.0 when the MRAM circuit is fabricated at a 65 nm CMOS process technology.
12. The cell of the MRAM circuit of claim 1 , wherein a cell size of the horizontal outer perimeter is defined by a pitch of one or more metal lines and by a size of the access transistor.
13. The cell of the MRAM circuit of claim 1 , wherein a first dimension of the horizontal outer perimeter comprises a value along a range of one hundred fourteen (114) nanometers (nm) to two hundred twenty (220) nanometers (nm).