Shift register, gate driving circuit, display apparatus and driving method

1. A shift register, comprising:

a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal;

a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal;

an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other;

a pull-down control sub-circuit, configured to control a potential of a pull-down node according to the first node; and

a pull-down sub-circuit, configured to pull down the first node and the output terminal to a non-operating potential under control of the pull-down node,

wherein

the pull-down control sub-circuit comprises a first pull-down control transistor and a second pull-down control transistor, wherein a first electrode of the first pull-down control transistor is connected with a control electrode of the first pull-down control transistor and connected to a pull-down control signal line, and a second electrode of the first pull-down control transistor is connected to the pull-down node, a first electrode of the second pull-down control transistor is connected to the pull-down node, a control electrode of the second pull-down control transistor is connected to the first node, and a second electrode of the second pull-down control transistor is connected to a pull-down signal line,

the pull-down sub-circuit comprises a first pull-down transistor and a second pull-down transistor, wherein a first electrode of the first pull-down transistor is connected to the first node, a control electrode of the first pull-down transistor is connected to the pull-down node, and a second electrode of the first pull-down transistor is connected to the pull-down signal line, a first electrode of the second pull-down transistor is connected to the output terminal, a control electrode of the second pull-down transistor is connected to the pull-down node, and a second electrode of the second pull-down transistor is connected to the pull-down signal line,

the first input sub-circuit comprises:

a charging sub-circuit, configured to input the first input signal to a blanking pull-up control node according to the first input signal;

a storing sub-circuit, having a first terminal connected to the blanking pull-up control node, configures to store a blanking pull-up control signal according to the first input signal; and

an isolating sub-circuit, configured to input the blanking output control signal to the first node according to the blanking pull-up control signal in the blanking period of time of a frame;

the isolating sub-circuit comprises a first isolating transistor and a second isolating transistor, wherein a control electrode of the first isolating transistor is connected to the blanking pull-up control node, a first electrode of the second isolating transistor is connected to a second electrode of the first isolating transistor, a second electrode of the second isolating transistor is connected to the first node, and a control electrode of the second isolating transistor is connected to an isolation control signal line,

the shift register further comprising:

an electric leakage prevention sub-circuit, configured to input an operating potential to the first electrode or the second electrode of the second isolating transistor under control of the first node and/or the blanking pull-up control node,

wherein the electric leakage prevention sub-circuit comprises a transistor configured for preventing electric leakage, wherein a control electrode of the transistor is connected to the control electrode of the second isolating transistor, a first electrode of the transistor is connected to the second electrode of the second isolation transistor, and a second electrode of the transistor is connected to the first node.

2. The shift register according to claim 1 , wherein

the first input sub-circuit is configured to receive the first input signal from the first input terminal, and input the blanking output control signal to the first node in a blanking period of time of the frame according to the first input signal, and

the second input sub-circuit is configured to receive the second input signal from the second input terminal, and input the display output control signal to the first node in a display period of the frame according to the second input signal.

3. The shift register according to claim 1 , further comprising:

a display reset sub-circuit, configured to reset the first node under control of a display reset control signal.

4. The shift register according to claim 3 , further comprising:

a blanking reset sub-circuit, configured to reset the first node and/or the output terminal under control of a blanking reset control signal before an end of the blanking period of time of the frame.

5. The shift register according to claim 1 , wherein the output sub-circuit comprises at least one shift signal output terminal and at least one pixel signal output terminal.

6. The shift register according to claim 1 , wherein

the charging sub-circuit comprises a charging transistor, having a first electrode and/or a control electrode connected to the first input terminal, and a second electrode connected to the blanking pull-up control node; and

the storing sub-circuit comprises a first capacitor, having a first terminal connected to the blanking pull-up control node.

7. The shift register according to claim 6 , wherein the electric leakage prevention sub-circuit comprises a second electric leakage prevention transistor, wherein a first electrode of the second electric leakage prevention transistor is connected to the second electrode of the charging transistor, a second electrode of the second electric leakage prevention transistor is connected to an electric leakage prevention signal input terminal, and a control electrode of the second electric leakage prevention transistor is connected to the blanking pull-up control node.

8. The shift register according to claim 1 , wherein

the second input sub-circuit comprises a first display input transistor, having a first electrode connected to the first node, a second electrode and/or a control electrode connected to the second input terminal; and

the output sub-circuit comprises an output transistor and an output capacitor, wherein a first electrode of the output transistor is connected to an output clock signal line, a second electrode of the output transistor is connected to the output terminal, and a control electrode of the output transistor is connected to the first node, a first terminal of the output capacitor is connected to the first node, and a second terminal of the output capacitor is connected to the output terminal.

9. The shift register according to claim 8 , wherein the second input sub-circuit further comprises a second display input transistor, having a first electrode and a gate electrode both connected to the first electrode of the first display input transistor, and a second electrode connected to the first node.

10. The shift register according to claim 3 , wherein

the display reset sub-circuit comprises a display reset transistor, having a first electrode connected to the first node, a control electrode connected to a display reset control terminal, and a second electrode connected to a display reset signal line.

11. The shift register according to claim 1 , wherein the electric leakage prevention sub-circuit comprises a transistor configured for preventing electric leakage, wherein a control electrode of the transistor is connected to the control electrode of the second isolating transistor, a first electrode of the transistor is connected to another transistor configured for preventing electric leakage, and a second electrode of the transistor is connected to the second isolating transistor.

12. The shift register according to claim 1 , wherein the electric leakage prevention sub-circuit comprises a transistor configured for preventing electric leakage, wherein a control electrode of the transistor is connected to the pull-down node, a first electrode of the transistor is connected to the first node, and a second electrode of the transistor is connected to a third signal line.

13. The shift register according to claim 1 , wherein the electric leakage prevention sub-circuit comprises a transistor configured for preventing electric leakage, wherein a control electrode of the transistor is connected to a display reset control terminal, a first electrode of the transistor is connected to the first node, and a second electrode of the transistor is connected to a second signal line.

14. A gate driving circuit, comprising N stages of shift registers, where N is an integer greater than 2, each of the shift registers being the shift register according to claim 1 ,

a second input terminal of a first stage shift register is connected to a display signal line, and a first input terminal of the first stage shift register is connected to a blanking signal line; and

a display reset control terminal of an N-th stage shift register is connected to a display reset signal line.

15. A display apparatus, comprising the gate driving circuit according to claim 14 .

16. A driving method applicable to the shift register according to claim 1 , comprising:

during a display period of time of the frame:

in a first control phase, inputting, by the second input sub-circuit, the display output control signal to the first node; and

in a first output phase, outputting, by the output sub-circuit, a first output signal under control of the first node, and

during the blanking period of time of the frame:

in a second control phase, inputting, by the first input sub-circuit, the blanking output control signal to the first node; and

in a second output phase, outputting, by the output sub-circuit, a second output signal under control of the first node.

17. The driving method according to claim 16 , further comprising:

in a display reset phase, resetting the first node under control of a display reset control signal.