Semiconductor memory device and operating method for performing program operation
A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period and controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.
1. A method of operating a semiconductor memory device, which comprises a plurality of program loops,
wherein at least some program loops among the plurality of program loops include:
determining a step voltage based on a comparison result of a threshold loop number and a current program loop number;
determining a program voltage based on the step voltage;
applying the program voltage to selected memory cells; and
performing a verify operation on the selected memory cells, and
wherein the determining of the step voltage includes determining the threshold loop number based on an initial program voltage applied in a first program loop among the plurality of program loops.
2. The method of claim 1 , wherein the determining of the step voltage further includes determining a first voltage as the step voltage, when the current program loop number is less than the threshold loop number, and
wherein the determining of the program voltage includes determining, as the program voltage of a current program loop, a value obtained by adding the step voltage to a previous program voltage of a previous program loop.
3. The method of claim 2 , wherein the determining of the step voltage further includes determining, as the step voltage, a second voltage different from the first voltage, when the current program loop number is not less than the threshold loop number.
4. The method of claim 3 , wherein the second voltage is lower than the first voltage.
5. The method of claim 2 , wherein the first program loop includes:
applying the initial program voltage to the selected memory cells;
counting a number of memory cells having threshold voltages greater than a reference voltage; and
determining the first voltage, based on the number of memory cells having the threshold voltages greater than the reference voltage.
6. The method of claim 1 , wherein the determining of the step voltage further includes:
counting a number of memory cells having threshold voltages greater than a reference voltage, when the current program loop number is less than the threshold loop number; and
determining the step voltage, based on the number of memory cells having the threshold voltages greater than the reference voltage, and
wherein the determining of the program voltage includes determining, as the program voltage of a current program loop, a value obtained by adding the step voltage to a previous program voltage of a previous program loop.
7. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; and
control logic configured to control the program operation of the peripheral circuit,
wherein the control logic:
controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period; and
controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period,
wherein the first program period includes first to kth program loops, and the second program period includes a (k+1)th program loop and program loops subsequent thereto,
wherein k is a natural number of 2 or more, and
wherein the control logic determines k based on a program start voltage applied in the first program loop.
8. The semiconductor memory device of claim 7 , wherein the first step voltage is greater than the second step voltage.
9. The semiconductor memory device of claim 7 , wherein the control logic determines the first step voltage, based on a number of memory cells having threshold voltages greater than a reference voltage, as a result obtained by performing the first program loop.
10. The semiconductor memory device of claim 9 , wherein the control logic changes the first step voltage, based on a number of memory cells having threshold voltages greater than the reference voltage, as a result obtained by performing the second program loop after the first program loop.
11. The semiconductor memory device of claim 9 , wherein the semiconductor memory device uses a lookup table for determining a first step voltage value corresponding to the number of memory cells having the threshold voltages greater than the reference voltage.