Approach for processing near-memory processing commands using near-memory register definition data
An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands. A particular combination of source and/or destination registers to be used to process a PIM command is specified by the PIM command or determined by a near-memory processing element processing the PIM command. According to another implementation, the PIM register definition data specifies an initial combination of source and/or destination registers and one or more update functions for each PIM command. A near-memory processing element processes a PIM command using the initial combination of source and/or destination registers and uses the one or more update functions to update the combination of source and/or destination registers to be used the next time the PIM command is processed.
1. An execution unit configured to process a command that contains a number that identifies a particular combination of multiple registers selected from a plurality of combinations of multiple registers, wherein:
the command does not contain an identifier of a register, and
the command is a near-memory processing command or a processing-in-memory (PIM) command.
2. The execution unit of claim 1 , further configured to process the command a second time using a different combination of multiple registers from the plurality of combinations of multiple registers.
3. The execution unit of claim 1 , wherein:
the execution unit is a PIM execution unit;
data that specifies the plurality of combinations of multiple registers is stored local to the PIM execution unit.
4. The execution unit of claim 1 , wherein the particular combination of multiple registers comprises a first register that is read by the command and a second register that is written by the command.
5. The execution unit of claim 1 , wherein the plurality of combinations of multiple registers is designated for the command.
6. The execution unit of claim 1 , wherein the execution unit is in a memory bank or a volatile memory module.
7. An execution unit configured to:
process a command that contains number that identifies a particular combination of multiple registers, wherein the command does not contain an identifier of a register; and
update the particular combination of multiple registers to specify a different register.
8. The execution unit of claim 7 , further configured to use one or more update functions to update the particular combination of multiple registers to specify a different register.
9. The execution unit of claim 8 , wherein the one or more update functions specify one or more of an increment amount or a decrement amount.
10. The execution unit of claim 8 , wherein the particular combination of multiple registers and the one or more update functions are specific to the command.
11. The execution unit of claim 8 , further configured to update the one or more update functions.
12. The execution unit of claim 7 , wherein:
the execution unit is a PIM execution unit;
data that specifies the particular combination of multiple registers is stored local to the PIM execution unit.
13. The execution unit of claim 7 , wherein the particular combination of multiple registers comprises a first register that is read by the command and a second register that is written by the command.
14. The execution unit of claim 7 , wherein:
the execution unit is a PIM execution unit;
data is stored local to the PIM execution unit that specifies, for each individual command of a plurality of commands, both a respective combination of multiple registers to be used to process the individual command, and one or more update functions for updating the respective combination of multiple registers.
15. The execution unit of claim 7 , wherein the execution unit is in a memory bank or a volatile memory module.
16. A processor configured to issue a command that contains number that identifies a particular combination of multiple registers, wherein:
the command does not contain an identifier of a register, and
the command causes a near-memory processing element to perform one or more computations using the particular combination of multiple registers.
17. The processor of claim 16 , further configured to send to the near-memory processing element, data that specifies one or more combinations of multiple registers, or one or more update functions to update one or more registers for the particular combination of multiple registers.
18. The processor of claim 17 , wherein the one or more update functions specify one or more of an increment amount or a decrement amount.