Insulating cap on contact structure
A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.
1. A semiconductor device structure, comprising:
a gate electrode layer formed over a substrate;
a conductive capping feature formed on and in direct contact with the gate electrode layer;
a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, wherein an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature; and
a first insulating capping feature formed over the air gap, wherein a sidewall surface of the first insulating capping feature is aligned with a sidewall surface of the conductive capping feature.
2. The semiconductor device structure as claimed in claim 1 , further comprising:
a gate spacer adjacent to the gate electrode layer, wherein the air gap is in direct contact with the gate spacer.
3. The semiconductor device structure as claimed in claim 2 , wherein the first insulating capping feature extends from a first position to a second position, the first position is on a sidewall of the gate spacer, and the second position is over a top surface of the S/D contact structure.
4. The semiconductor device structure as claimed in claim 3 , wherein the first insulating capping feature has a reversed U-shaped profile.
5. The semiconductor device structure as claimed in claim 3 , wherein the first insulating capping feature comprises:
a first capping layer; and
a second capping layer formed over the first capping layer or below the first capping layer.
6. The semiconductor device structure as claimed in claim 3 , wherein the first insulating capping feature comprises:
a first capping layer; and
a second capping layer covering opposite sidewalls of the first capping layer and an upper sidewall of the S/D contact structure.
7. The semiconductor device structure as claimed in claim 1 , wherein a top surface of the air gap is lower than a top surface of the gate electrode layer.
8. The semiconductor device structure as claimed in claim 1 , wherein the air gap is in direct contact with the S/D contact structure.
9. A semiconductor device structure, comprising:
a fin formed over a substrate;
a gate dielectric layer formed over the fin;
a gate electrode layer formed over the gate dielectric layer;
a source/drain (S/D) contact structure formed adjacent to the gate electrode layer; and
a first insulating capping feature formed adjacent to the S/D contact structure, wherein an air gap is formed below the first insulating capping feature, and an outermost sidewall surface of the first insulating capping feature is aligned with a sidewall surface of the gate dielectric layer, and a top surface of the gate dielectric layer is higher than a top surface of the air gap.
10. The semiconductor device structure as claimed in claim 9 , wherein the first insulating capping feature has a protruding portion which extends into a space between the gate dielectric layer and the S/D contact structure.
11. The semiconductor device structure as claimed in claim 10 , wherein the protruding portion of the first insulating capping feature isolates the gate dielectric layer from the S/D contact structure.
12. The semiconductor device structure as claimed in claim 9 , wherein the first insulating capping feature has a main portion and a protrusion portion, a sidewall of the main portion is close to the gate electrode layer than a sidewall of the protrusion portion.
13. The semiconductor device structure as claimed in claim 9 , wherein the first insulating capping feature is in direct contact with the top surface of the gate dielectric layer.
14. The semiconductor device structure as claimed in claim 9 , further comprising:
a via structure formed over the gate electrode layer, wherein a top surface of the first insulating capping feature is higher than a bottom surface of the via structure.
15. The semiconductor device structure as claimed in claim 9 , further comprising:
an insulating layer formed over the first insulating capping feature, wherein the insulating layer is in direct contact with the first insulating capping feature.
16. A semiconductor device structure, comprising:
a gate electrode layer formed over a substrate;
a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer;
a first insulating capping feature formed on the S/D contact structure, wherein the first insulating capping feature has an extending portion; and
an air gap formed adjacent to the S/D contact structure, wherein the air gap is directly below and in direct contact with the extending portion of the first insulating capping feature, and a top surface of the gate electrode layer is lower than a top surface of the S/D contact structure.
17. The semiconductor device structure as claimed in claim 16 , further comprising:
a conductive capping feature formed on and in direct contact with the gate electrode layer, wherein the air gap is lower than a top surface of the conductive capping feature.
18. The semiconductor device structure as claimed in claim 17 , wherein a sidewall surface of the conductive capping feature is aligned with a sidewall surface of the first insulating capping feature.
19. The semiconductor device structure as claimed in claim 16 , further comprising:
a gate spacer adjacent to the gate electrode layer, wherein the gate spacer is in direct contact with the air gap.
20. The semiconductor device structure as claimed in claim 16 , further comprising:
a via structure formed over the gate electrode layer, wherein a top surface of the first insulating capping feature is higher than a bottom surface of the via structure.