Granted Patent B2

US 12,724,845 · App. 17/847,887 · Granted Sep 1, 2026

Inventors: Christopher N. Peters (Nashua, NH); David D. Moser (Haymarket, VA)

Assignee: BAE Systems Information and Electronic Systems Integration Inc.

G06F17/142H03H17/0223H04B1/18

Abstract

Claims (29)

1 . A reconfigurable channelizer comprising:

a polyphase filter circuit configured to filter time domain input data to control spectral shaping of frequency bins of the reconfigurable channelizer's output, wherein filter coefficients and a quantity of folds of the polyphase filter circuit are dynamically programmable;

a fast Fourier transform (FFT) circuit configured to transform the filtered time domain input data to output frequency domain data distributed into the frequency bins, wherein a quantity of the frequency bins is dynamically programmable;

wherein the FFT circuit comprises:

a sample reorder circuit and two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage;

a first channel circuit configured to transform a first phase of the filtered time domain input data to a first phase of the frequency domain data; and

a second channel circuit configured to transform a second phase of the filtered time domain input data to a second phase of the frequency domain data, wherein at each stage, the first channel circuit and the second channel circuit share the butterfly circuit associated with that stage.

2 . The reconfigurable channelizer of claim 1 , wherein the FFT circuit is employed to implement an inverse fast Fourier transform.

3 . The reconfigurable channelizer of claim 1 , wherein the FFT circuit comprises five serially cascaded processing stages, the five serially cascaded processing stages including a 64-point stage, a 128-point stage, a 256-point stage, a 512-point stage, and a 1024 point stage.

4 . The reconfigurable channelizer of claim 1 , wherein the reconfigurable channelizer comprises a two phase reorder circuit configured to split the filtered time domain input data into the first phase of the filtered time domain input data and the second phase of the filtered time domain input data.

5 . The reconfigurable channelizer of claim 1 , wherein the reconfigurable channelizer comprises a two phase merge circuit configured to merge the first phase of the frequency domain data with the second phase of the frequency domain data to generate the output frequency domain data.

6 . The reconfigurable channelizer of claim 1 , wherein the polyphase filter circuit comprises a crossbar circuit configured to align the time domain input data with the filter coefficients and a multiply circuit configured to multiply the aligned time domain input data with the filter coefficients.

7 . The reconfigurable channelizer of claim 1 , wherein the reconfigurable channelizer is configured to generate the frequency bins for output at a rate equal to two times a frequency spacing between the frequency bins.

8 . The reconfigurable channelizer of claim 1 , wherein the quantity of the frequency bins is dynamically programmable to one of 64, 128, 256, 512, or 1024, and the quantity of folds of the polyphase filter circuit is dynamically programmable in a range of one to seven.

9 . The reconfigurable channelizer of claim 1 , wherein the reconfigurable channelizer output frequency domain data is organized into frames, the frames of length proportional to the quantity of the frequency bins.

10 . The reconfigurable channelizer of claim 1 , wherein the reconfigurable channelizer is implemented in an application specific integrated circuit.

11 . A receiver comprising:

an analog to digital converter (ADC) configured to convert a received analog signal to a time domain digital signal; and

a reconfigurable channelizer configured to convert the time domain digital signal to output frequency domain data distributed into a quantity of frequency bins of the reconfigurable channelizer's output, the reconfigurable channelizer including

a polyphase filter circuit configured to filter the time domain digital signal to control spectral shaping of the frequency bins of the reconfigurable channelizer's output, wherein filter coefficients and a quantity of folds of the polyphase filter circuit are dynamically programmable, and

a fast Fourier transform (FFT) circuit configured to transform the filtered time domain digital signal to the frequency domain data distributed into the frequency bins, wherein the quantity of the frequency bins is dynamically programmable;

wherein the FFT circuit comprises:

a sample reorder circuit and two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage;

a first channel circuit configured to transform a first phase of the filtered time domain digital signal to a first phase of the frequency domain data; and

a second channel circuit configured to transform a second phase of the filtered time domain digital signal to a second phase of the frequency domain data, wherein at each stage, the first channel circuit and the second channel circuit share the butterfly circuit associated with that stage.

12 . The receiver of claim 11 , wherein the FFT circuit comprises five serially cascaded processing stages, the five serially cascaded processing stages including a 64 -point stage, a 128-point stage, a 256-point stage, a 512-point stage, and a 1024 point stage.

13 . The receiver of claim 11 , wherein the reconfigurable channelizer comprises: a two phase reorder circuit configured to split the filtered time domain digital signal into the first phase of the filtered time domain digital signal and the second phase of the filtered time domain digital signal; and a two phase merge circuit configured to merge the first phase of the frequency domain data with the second phase of the frequency domain data to generate the output frequency domain data.

14 . The receiver of claim 11 , wherein the quantity of the frequency bins is dynamically programmable to one of 64, 128, 256, 512or 1024, and the quantity of folds of the polyphase filter circuit is dynamically programmable in a range of one to seven, and the reconfigurable channelizer's output frequency domain data is organized into frames, the frames of length proportional to the quantity of the frequency bins.

15 . The receiver of claim 11 , wherein the ADC and the reconfigurable channelizer are implemented in an application specific integrated circuit.

Assignments (1)

Continuity (1)

References Cited (27)