Silicon carbide based integrated passive devices for impedence matching of radio frequency power devices and process of implementing the same

1 . An amplifier circuit, comprising:

an RF amplifier;

an impedance matching network;

a fundamental frequency matching circuit;

a higher order harmonic termination circuit; and

an integrated passive device (IPD) comprising a silicon carbide (SiC) substrate,

wherein the integrated passive device (IPD) comprises one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

2 . The amplifier circuit of claim 1 , wherein the one or more reactive components of the fundamental frequency matching circuit comprise at least one second capacitor implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one second capacitor comprises a second top metal and a second bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

3 . The amplifier circuit of claim 1 , wherein the one or more reactive components of the higher order harmonic termination circuit comprise at least one first capacitor and at least one first inductor connected in parallel along a parallel branch implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one first capacitor comprises a first top metal and a first bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

4 . The amplifier circuit of claim 1 ,

wherein the one or more reactive components of the fundamental frequency matching circuit comprise at least one second capacitor implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD);

wherein the one or more reactive components of the higher order harmonic termination circuit comprise at least one first capacitor and at least one first inductor connected in parallel along a parallel branch implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one first capacitor comprises a first top metal and a first bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

5 . The amplifier circuit of claim 4 ,

wherein the fundamental frequency matching circuit comprises the at least one second capacitor and at least one second inductor connected in series along the parallel branch;

wherein the one or more reactive components of the fundamental frequency matching circuit comprise the at least one second capacitor; and

wherein the at least one second capacitor comprises a second top metal and a second bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

6 . The amplifier circuit of claim 5 ,

wherein the higher order harmonic termination circuit comprises a parallel LC resonator connected in series between the at least one second inductor and the at least one second capacitor, the parallel LC resonator comprising the at least one second capacitor connected in parallel with the at least one first inductor; and

wherein the one or more reactive components of the higher order harmonic termination circuit comprise the at least one first capacitor and the at least one first inductor.

7 . The amplifier circuit of claim 5 , wherein the integrated passive device (IPD) is configured to form the at least one first inductor with a metallization arranged on a surface of the silicon carbide (SiC) substrate.

8 . The amplifier circuit of claim 1 , wherein the integrated passive device (IPD) comprises:

a first top metal; and

a first bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one first capacitor with the first top metal and the first bottom metal having a dielectric layer therebetween.

9 . The amplifier circuit of claim 1 , wherein the integrated passive device (IPD) comprises:

a second top metal; and

a second bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one second capacitor with the second top metal and the second bottom metal having a dielectric layer therebetween.

10 . The amplifier circuit according to claim 9 wherein the integrated passive device (IPD) comprises:

a bottom metallization on a bottom of the silicon carbide (SiC) substrate; and

at least one via electrically connected to the bottom metallization and the second bottom metal.

11 . The amplifier circuit of claim 1 , wherein the integrated passive device (IPD) comprises:

a first top metal;

a first bottom metal;

a second top metal; and

a second bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one first capacitor with the first top metal and the first bottom metal having a dielectric layer therebetween; and

wherein the integrated passive device (IPD) is configured to form at least one second capacitor with the second top metal and the second bottom metal having a dielectric layer therebetween.

12 . The amplifier circuit of claim 1 , wherein the integrated passive device (IPD) additionally comprises one or more reactive components of an impedance matching network on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

13 . The amplifier circuit of claim 1 , wherein:

the RF amplifier comprises a first terminal, a second terminal, and a reference potential terminal, the RF amplifier configured to amplify an RF signal across an RF frequency range that includes a fundamental RF frequency;

the amplifier circuit further comprises a parallel branch connected in parallel with the first terminal and the reference potential terminal of the RF amplifier, the parallel branch comprising a fundamental frequency matching circuit;

the impedance matching network comprises: a series branch connected in series between a first port of the amplifier circuit and the first terminal of the RF amplifier; and

the higher order harmonic termination circuit electrically connected in series with the fundamental frequency matching circuit.

14 . A process of implementing an amplifier circuit, comprising:

implementing an RF amplifier;

implementing an impedance matching network;

implementing fundamental frequency matching circuit;

implementing a higher order harmonic termination circuit; and

configuring an integrated passive device (IPD) with a silicon carbide (SiC) substrate,

wherein the integrated passive device (IPD) comprises one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

15 . An integrated circuit, comprising:

an integrated passive device (IPD) comprising a silicon carbide (SiC) substrate,

wherein the integrated passive device (IPD) comprises one or more reactive components of a fundamental frequency matching circuit and one or more reactive components of a higher order harmonic termination circuit.

16 . The integrated circuit of claim 15 ,

wherein the one or more reactive components of the fundamental frequency matching circuit comprise at least one second capacitor implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one second capacitor comprises a second top metal and a second bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

17 . The integrated circuit of claim 16 ,

wherein the one or more reactive components of the higher order harmonic termination circuit comprise at least one first capacitor and at least one first inductor connected in parallel along a parallel branch implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one first capacitor comprises a first top metal and a first bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

18 . The integrated circuit of claim 15 ,

wherein the one or more reactive components of the fundamental frequency matching circuit comprise at least one second capacitor implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD);

wherein the one or more reactive components of the higher order harmonic termination circuit comprise at least one first capacitor and at least one first inductor connected in parallel along a parallel branch implemented on the silicon carbide (SiC) substrate of the integrated passive device (IPD); and

wherein the at least one first capacitor comprises a first top metal and a first bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

19 . The integrated circuit of claim 18 ,

wherein the fundamental frequency matching circuit comprises the at least one second capacitor and at least one second inductor connected in series along the parallel branch;

wherein the one or more reactive components of the fundamental frequency matching circuit comprise the at least one second capacitor; and

wherein the at least one second capacitor comprises a second top metal and a second bottom metal with a dielectric layer therebetween on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).

20 . The integrated circuit of claim 19 ,

wherein the higher order harmonic termination circuit comprises a parallel LC resonator connected in series between the at least one second inductor and the at least one second capacitor, the parallel LC resonator comprising the at least one second capacitor connected in parallel with at least one first inductor; and

wherein the one or more reactive components of the higher order harmonic termination circuit comprise the at least one first capacitor and the at least one first inductor.

21 . The integrated circuit of claim 19 , wherein the integrated passive device (IPD) is configured to form the at least one first inductor with a metallization arranged on a surface of the silicon carbide (SiC) substrate.

22 . The integrated circuit of claim 15 , wherein the integrated passive device (IPD) comprises:

a first top metal; and

a first bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one first capacitor with the first top metal and the first bottom metal having a dielectric layer therebetween.

23 . The integrated circuit of claim 15 , wherein the integrated passive device (IPD) comprises:

a second top metal; and

a second bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one second capacitor with the second top metal and the second bottom metal having a dielectric layer therebetween.

24 . The integrated circuit according to claim 23 wherein the integrated passive device (IPD) comprises:

a bottom metallization on a bottom of the silicon carbide (SiC) substrate; and

at least one via electrically connected to the bottom metallization and the second bottom metal.

25 . The integrated circuit of claim 15 , wherein the integrated passive device (IPD) comprises:

a first top metal;

a first bottom metal;

a second top metal; and

a second bottom metal,

wherein the integrated passive device (IPD) is configured to form at least one first capacitor with the first top metal and the first bottom metal having a dielectric layer therebetween; and

wherein the integrated passive device (IPD) is configured to form at least one second capacitor with the second top metal and the second bottom metal having a dielectric layer therebetween.

26 . The integrated circuit of claim 15 , wherein the integrated passive device (IPD) additionally comprises one or more reactive components of an impedance matching network on an upper surface of the silicon carbide (SiC) substrate of the integrated passive device (IPD).