Multi-channel spectrum analyzer with multi-channel analog-digital-converters (ADCs)

1. A multi-channel analog-digital converter (ADC) subsystem for a radio frequency (RF) test device, comprising:

a plurality of multi-channel ADCs to receive one or more down-converted signals and convert the one or more received signals to one or more digital output signals;

a field programmable gate array (FPGA) to select one or more ADCs among the plurality of ADCs based, at least in part, on a characteristic of each received signal and a characteristic of each ADC among the plurality of ADCs; and

an ADC sample clock to provide a clock signal to the selected one or more ADCs.

2. The multi-channel ADC subsystem of claim 1 , wherein the characteristic of each received signal comprises one or more of a frequency, a bandwidth, and a signal type.

3. The multi-channel ADC subsystem of claim 1 , wherein the characteristic of each ADC among the plurality of ADCs comprises one or more of a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and a spurious free dynamic range (SFDR).

4. The multi-channel ADC subsystem of claim 1 , wherein a frequency of the clock signal to be provided to the selected one or more ADCs is selected based on a type of the selected one or more ADCs.

5. The multi-channel ADC subsystem of claim 4 , wherein the frequency of the clock signal is selected by a central processing unit (CPU) of the RF test device or the FPGA.

6. The multi-channel ADC subsystem of claim 1 , wherein the ADC sample clock comprises an oscillator, a direct digital synthesizer, and a filter.

7. The multi-channel ADC subsystem of claim 1 , wherein the FPGA is further to select one or more inputs of a selected ADC to receive the one or more down-converted signals.

8. A test device to analyze radio frequency (RF) signals, comprising:

a front end to receive one or more RF signals and pre-process the received RF signals;

a mixer to down-convert the pre-processed RF signals;

a multi-channel analog-digital converter (ADC) subsystem to receive the down-converted signals from the mixer and convert to digital output signals, wherein the multi-channel ADC subsystem comprises:

a plurality of multi-channel ADCs;

a field programmable gate array (FPGA) to select one or more ADCs among the plurality of ADCs based, at least in part, on a characteristic of each received RF signal and a characteristic of each ADC among the plurality of ADCs; and

an ADC sample clock to provide a clock signal to the selected one or more ADCs; and

one or more operational subsystems to perform analytical operations on the digital output signals.

9. The test device of claim 8 , wherein the front end comprises an attenuator and a filter.

10. The test device of claim 8 , wherein the one or more operational subsystems include at least one of a display subsystem, an analysis subsystem, a fast Fourier transform (FFT) subsystem, or a storage subsystem.

11. The test device of claim 8 , wherein the characteristic of each received RF signal comprises one or more of a frequency, a bandwidth, and a signal type.

12. The test device of claim 8 , wherein the characteristic of each ADC among the plurality of ADCs comprises one or more of a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and a spurious free dynamic range (SFDR).

13. The test device of claim 8 , wherein a frequency of the clock signal to be provided to the selected one or more ADCs is selected based on a type of the selected one or more ADCs.

14. The test device of claim 8 , wherein the FPGA comprises one or more digital processing circuitry to receive and process the digital output signals.

15. The test device of claim 8 , wherein the test device is a spectrum analyzer.

16. A method, comprising:

receiving one or more down-converted signals from a mixer of a test device;

selecting, by a field programmable gate array (FPGA) of the test device, one or more analog-digital converters (ADCs) among a plurality of ADCs based, at least in part, on a characteristic of each received RF signal and a characteristic of each ADC among the plurality of ADCs; and

converting the one or more down-converted signals to digital output signals using the selected one or more ADCs.

17. The method of claim 16 , further comprising:

selecting one or more inputs of a selected ADC to receive the one or more down-converted signals.

18. The method of claim 17 , further comprising:

receiving a frequency and a bandwidth associated with an input RF signal from a user; and

selecting the one or more ADCs or the one or more inputs of a selected ADC based, at least in part, on the received frequency and bandwidth from the user.

19. The method of claim 18 , further comprising:

selecting the one or more ADCs or the one or more inputs of the selected ADC by employing a matching table stored in the FPGA.

20. The method of claim 16 , wherein

the characteristic of each received RF signal comprises one or more of a frequency, a bandwidth, and a signal type, and

the characteristic of each ADC among the plurality of ADCs comprises one or more of a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and a spurious free dynamic range (SFDR).