Methods of reducing capacitance in field-effect transistors

1. A method, comprising:

forming a high-k metal gate stack (HKMG) over a semiconductor fin, wherein the high-k metal gate stack (HKMG) comprises a high-k dielectric layer and a work function layer over the high-k dielectric layer;

after the forming of the high-k metal gate stack (HKMG), forming a trench to separate the HKMG into two portions;

depositing a first dielectric layer in the trench by implementing a deposition process at a first deposition rate;

forming a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer is different from the first dielectric layer in composition;

recessing a portion of the second dielectric layer;

depositing a third dielectric layer over the recessed second dielectric layer by implementing the deposition process at a second deposition rate higher than the first deposition rate, wherein the third dielectric layer is different from the second dielectric layer in composition; and

planarizing the third dielectric layer to form a gate isolation feature.

2. The method of claim 1 , wherein dielectric constant of the second dielectric layer is less than dielectric constant of each of the first and the third dielectric layers.

3. The method of claim 1 , wherein composition of the third dielectric layer is the same as composition of the first dielectric layer.

4. The method of claim 1 , wherein the forming of the second dielectric layer comprises implementing a flowable chemical vapor deposition (FCVD) process.

5. The method of claim 4 , further comprising:

after the forming of the second dielectric layer and before the recessing of the portion of the second dielectric layer, curing the second dielectric layer.

6. The method of claim 4 , wherein the deposition process comprises an atomic layer deposition (ALD) process, a chemical vapor deposition process (CVD), or a combination thereof.

7. The method of claim 1 , wherein a bottom surface of the trench is below a bottom surface of the fin.

8. The method of claim 1 , wherein the HKMG is a first HKMG, and the method further comprises:

forming a second HKMG over the semiconductor fin,

wherein the gate isolation feature further cuts the second HKMG into two portions.

9. A method, comprising:

providing a workpiece comprising a first fin and a second fin protruding from a substrate, the first fin and the second fin extending lengthwise along a first direction and isolated from each other by an isolation feature;

forming a gate structure over the first fin and the second fin, the gate structure extending lengthwise along a second direction that is substantially perpendicular to the first direction;

performing an etching process to form a trench extending vertically through the gate structure and the isolation feature and disposed between the first fin and the second fin, wherein the trench extends lengthwise along the first direction;

depositing a first dielectric layer in the trench;

forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is different from the first dielectric layer in composition; and

forming a third dielectric layer, wherein the third dielectric layer directly contacts a top portion of the second dielectric layer and a sidewall of the first dielectric layer.

10. The method of claim 9 , further comprising: after the forming of the second dielectric layer, curing the second dielectric layer.

11. The method of claim 9 , wherein dielectric constant of the second dielectric layer is less than dielectric constant of each of the first and the third dielectric layers.

12. The method of claim 9 , wherein composition of the third dielectric layer is the same as composition of the first dielectric layer.

13. The method of claim 9 , wherein the forming of the second dielectric layer comprises implementing a flowable chemical vapor deposition (FCVD) process.

14. The method of claim 9 , wherein the forming of the third dielectric layer comprises:

removing a portion of the second dielectric layer to partially expose the sidewall of the first dielectric layer; and

forming the third dielectric layer on the second dielectric layer to directly contact the exposed sidewall of the first dielectric layer.

15. The method of claim 9 , wherein the second dielectric layer includes an air gap, and wherein forming the third dielectric layer includes depositing a dielectric material over the first dielectric layer, thereby sealing an opening of the trench to form the air gap.

16. The method of claim 15 , wherein the dielectric material is a first dielectric material and is deposited over the workpiece at a first deposition rate, and wherein forming the first dielectric layer includes depositing a second dielectric material at a second deposition rate different from the first deposition rate.

17. A method, comprising:

forming a semiconductor fin over a substrate;

forming a first metal gate structure and a second metal gate structure separated from the first metal gate structure over the semiconductor fin, both the first metal gate structure and the second metal gate structure comprising a high-k dielectric layer and a work function layer over the high-k dielectric layer; and

forming a gate cut feature, including:

forming a trench in the first and the second metal gate structures;

depositing a first dielectric layer in the trench;

forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is different from the first dielectric layer in composition; and

forming a third dielectric layer over the second dielectric layer, wherein the third dielectric layer directly contacts a sidewall of the first dielectric layer, and

wherein the depositing of the first dielectric layer comprises implementing a first deposition process at a first deposition rate, and the forming of the third dielectric layer comprises implementing the first deposition process at a second deposition rate higher than the first deposition rate.

18. The method of claim 17 , wherein dielectric constant of the second dielectric layer is less than dielectric constant of each of the first and the third dielectric layers.

19. The method of claim 17 , wherein composition of the third dielectric layer is the same as composition of the first dielectric layer.

20. The method of claim 17 , wherein the forming of the second dielectric layer comprises implementing a flowable chemical vapor deposition (FCVD) process.