Read clock start and stop for synchronous memories
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
1. A memory controller, comprising:
a command queue including a plurality of entries for holding incoming memory access commands;
an arbiter for selecting commands from the command queue for dispatch to a memory; and
a read clock control circuit for monitoring read commands selected for dispatch to the memory, and responsive to a designated condition, commanding the memory to change a state of a read clock from a first state in which the read clock remains active following a postamble period for a read command, to a second state in which the read clock becomes inactive following the postamble period.
2. The memory controller of claim 1 , wherein:
said designated condition is that a gap of at least a predetermined size will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.
3. The memory controller of claim 1 , wherein:
said designated condition is that at least a designated number of write commands will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.
4. The memory controller of claim 1 , wherein:
said designated condition is that a current read command is a final command in a streak of read commands selected by the arbiter.
5. The memory controller of claim 1 , wherein:
said read clock control circuit commands the memory to change the state of the read clock by setting a read clock flag associated with a current read command to a designated value.
6. The memory controller of claim 1 , wherein:
said read clock control circuit commands the memory to change the state of the read clock by sending an explicit command to the memory separate from a read command.
7. The memory controller of claim 1 , wherein:
said read clock control circuit, responsive to the absence of said designated condition, causes read clock remains in the first state.
8. The memory controller of claim 7 , wherein:
wherein causing the read clock to remain in the first state comprises setting a read clock flag associated with a current read command to a designated value.
9. A method comprising:
at a memory controller, selecting memory access commands and dispatching them to a memory;
monitoring read commands selected for dispatch to the memory; and
commanding the memory to change a state of a read clock from a first state in which the read clock remains active following a postamble period for a read command, to a second state in which the read clock becomes inactive following the postamble period.
10. The method of claim 9 , wherein:
commanding the memory to change the state of the read clock is based on a designated condition, and said designated condition is that a gap of at least a predetermined size will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.
11. The method of claim 9 , wherein:
commanding the memory to change the state of the read clock is based on a designated condition, and said designated condition is that at least a designated number of write commands will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.
12. The method of claim 9 , wherein:
commanding the memory to change the state of the read clock is based on a designated condition, and said designated condition is that a current read command is a final command in a streak of read commands selected by the memory controller.
13. The method of claim 9 , wherein:
commanding the memory to change the state of the read clock includes setting a read clock flag associated with a current read command to a designated value.
14. The method of claim 9 , wherein:
commanding the memory to change the state of the read clock is based on a designated condition, and further comprising responsive to the absence of said designated condition, causing the read clock remains in the first state.
15. The method of claim 14 , wherein:
wherein causing the read clock to remain in the first state comprises setting a metadata flag associated with a current read command to a designated value.
16. The method of claim 9 , further comprising:
outputting a read clock signal from the memory for a read command response, wherein said outputting comprises:
toggling said read clock signal during a read preamble period;
transmitting data indicated by said read clock signal; and
toggling said read clock signal for at least a read postamble period.
17. The method of claim 16 , wherein:
said toggling said read clock signal for at least said read postamble period comprises stopping said toggling after said read postamble period in response to being in said first state.
18. A data processing system comprising:
a memory; and
an integrated circuit including a data processor and a memory controller coupled to the data processor and the memory, the memory controller comprising:
a command queue including a plurality of entries for holding incoming memory access commands;
an arbiter for selecting commands from the command queue for dispatch to the memory; and
a read clock control circuit for monitoring read commands selected for dispatch to the memory, and responsive to a designated condition, commanding the memory to change a state of a read clock from a first state in which the read clock remains active following a postamble period for a read command, to a second state in which the read clock becomes inactive following the postamble period.
19. The data processing system of claim 18 , wherein:
said designated condition is that a gap of at least a predetermined size will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.
20. The data processing system of claim 18 , wherein:
said designated condition is that at least a designated number of write commands will appear between a current read command dispatched to the memory and a subsequent read command to be dispatched to the memory.