Error compensation circuit for analog capacitor memory circuits
View Patent ↗An error compensation circuit for analog capacitor memory circuits includes a first transistor and a second transistor with gates connected respectively to top and bottom of an analog memory capacitor to read a voltage charged in the analog memory capacitor; a first switch and a second switch connected respectively to the first transistor and the second transistor to select the voltage to read; a first capacitor and a second capacitor to charge an electric charge to compensate or refresh the analog memory capacitor according to on/off of the first switch and the second switch; and an input terminal connected to sources of the first transistor and the second transistor to apply the voltage to operate the circuit. Accordingly, it is possible to compensate for an unintended phenomenon of the analog capacitor memory or refresh a change in memory value caused by leakage.
1. An error compensation circuit for analog capacitor memory circuits, comprising:
a first transistor and a second transistor with gates connected respectively to top and bottom of an analog memory capacitor to read a voltage charged in the analog memory capacitor;
a first switch and a second switch connected respectively to the first transistor and the second transistor to select the voltage to read;
a first capacitor and a second capacitor to charge an electric charge to compensate or refresh the analog memory capacitor according to on/off of the first switch and the second switch; and
an input terminal connected to sources of the first transistor and the second transistor to apply the voltage to operate the circuit.
2. The error compensation circuit for analog capacitor memory circuits according to claim 1 , further comprising:
a third switch and a fourth switch to determine a power line for charging the first capacitor and the second capacitor.
3. The error compensation circuit for analog capacitor memory circuits according to claim 2 , wherein a first signal is applied to the third switch and the second switch, and a second signal is applied to the fourth switch and the second switch.
4. The error compensation circuit for analog capacitor memory circuits according to claim 3 , wherein when the first signal is applied to the circuit, the voltage charged in the second capacitor is applied to the analog memory capacitor to refresh a stored value.
5. The error compensation circuit for analog capacitor memory circuits according to claim 4 , wherein an amount of electric charge is supplied as much as a difference in the voltage applied to the first capacitor at a size ratio of the first capacitor and the analog memory capacitor to compensate for the analog memory capacitor.
6. The error compensation circuit for analog capacitor memory circuits according to claim 3 , wherein when the second signal is applied to the circuit, the voltage charged in the first capacitor is applied to the analog memory capacitor to refresh a stored value.
7. The error compensation circuit for analog capacitor memory circuits according to claim 6 , wherein an amount of electric charge is supplied as much as a difference of the voltage applied to the second capacitor at a size ratio of the second capacitor and the analog memory capacitor to compensate for the analog memory capacitor.
8. The error compensation circuit for analog capacitor memory circuits according to claim 1 , further comprising:
a fifth switch and a sixth switch to block interference between the analog memory capacitor and a peripheral circuit.
9. The error compensation circuit for analog capacitor memory circuits according to claim 1 , wherein the input terminal applies a voltage of VDD or 0.
10. The error compensation circuit for analog capacitor memory circuits according to claim 1 , which is connected to an external circuit.