Refresh determination using memory cell patterns
A system includes a memory array having pattern cells and data cells. The pattern cells are configured to store only a first logic state. The data cells are configured to store the first logic state or a second logic state. Bias circuitry is configured to apply voltages to the pattern cells and data cells. Sensing circuitry is configured to read the pattern cells. A controller is configured to apply, using the bias circuitry, first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh a codeword; and apply, using the bias circuitry, the refresh of the codeword.
1. A system comprising:
a memory array comprising pattern cells and data cells, wherein each of the pattern cells is configured to store only a first logic state;
sensing circuitry configured to read the pattern cells; and
a controller configured to:
store a codeword in the data cells;
apply first voltages to the pattern cells;
determine, using the sensing circuitry, that at least a portion of the pattern cells switch;
determine, based on the portion of the pattern cells that switch, to refresh the codeword; and
apply the refresh of the codeword.
2. The system of claim 1 , wherein the first voltages to the pattern cells are biased higher than a read voltage applied to the data cells.
3. The system of claim 1 , wherein the controller is further configured to determine a logic state for each of the data cells.
4. The system of claim 3 , wherein the controller is further configured to, using bias circuitry, program at least a first portion of the data cells by changing a logic state of each data cell of the first portion.
5. The system of claim 1 , wherein:
the pattern cells are configured as a plurality of groups including a first group and a second group; and
the codeword refresh is determined based on whether the first group or the second group has switched.
6. The system of claim 1 , wherein:
the pattern cells are configured as a plurality of groups including a first group and a second group; and
the codeword refresh is determined based on whether the first group and the second group have switched.
7. The system of claim 1 , wherein:
the pattern cells are configured as a plurality of groups; and
the codeword refresh is determined based on whether at least 50% of the plurality of groups has switched.
8. The system of claim 7 , wherein the switching of a first group of the plurality of groups is determined based on whether a number of pattern cells in the first group that switch is greater than a threshold.
9. The system of claim 1 , wherein:
each of the data cells is configured to store the first logic state or a second logic state; and
the first logic state corresponds to a magnitude of threshold voltage that is greater than a magnitude of threshold voltage corresponding to the second logic state.
10. The system of claim 1 , wherein the controller is further configured to:
receive a read command from a host device; and
in response to receiving the read command, perform a read operation to retrieve data from the memory array.
11. The system of claim 1 , wherein:
applying the first voltages to the pattern cells comprises applying ramps in parallel to groups of the pattern cells.
12. The system of claim 1 , wherein:
applying the first voltages to the pattern cells comprises applying steps in parallel to groups of the pattern cells.
13. The system of claim 1 , wherein:
applying the first voltages to the pattern cells comprises applying a voltage to a single group of the pattern cells; and
the voltage applied to the single group is higher than a read voltage applied to the data cells.
14. The system of claim 1 , wherein:
applying the first voltages to the pattern cells comprises applying different respective voltages to each of multiple groups of the pattern cells; and
the respective voltage for each group is higher than a read voltage applied to the data cells.
15. A device comprising:
a memory array comprising data cells and pattern cells, wherein each of the pattern cells is configured to store only a first logic state; and
a controller configured to:
store a codeword in the data cells;
apply first voltages to the pattern cells;
determine that at least a portion of the pattern cells switch;
determine, based on the portion of the pattern cells that switch, to refresh the codeword; and
apply the refresh of the codeword.
16. The device of claim 15 , wherein the memory array has a vertical array architecture comprising vertical bitlines or digit lines intersecting a plurality of horizontal decks of wordlines.
17. The device of claim 16 , wherein each deck is configured as two interdigitated wordline combs so that each bitline or digit line forms two cells at each of the decks.
18. The device of claim 15 , wherein applying the first voltages comprises applying a voltage greater than a read voltage applied to the data cells.
19. The device of claim 15 , wherein the controller is further configured to determine a logic state for each of the data cells.
20. The device of claim 19 , wherein the controller is further configured to, using bias circuitry, program at least a first portion of the data cells by changing each data cell of the first portion from the first logic state to a second logic state, or from the second logic state to the first logic state.
21. The device of claim 20 , wherein the first logic state corresponds to a magnitude of threshold voltage that is greater than a magnitude of threshold voltage corresponding to the second logic state.