Approach for managing near-memory processing commands from multiple processor threads to prevent interference at near-memory processing elements
An approach is provided for managing near-memory processing commands (“PIM commands”) from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.
1. A memory controller configured to:
issue one or more near-memory processing commands for a first processor thread; and
defer issuance of one or more near-memory processing commands for a second processor thread by performing one of:
moving the one or more near-memory processing commands for the second processor thread into deferred command storage, or
changing a pointer to skip the one or more near-memory processing commands for the second processor thread;
wherein the one or more near-memory processing commands for the first processor thread and the one or more near-memory processing commands for the second processor thread are directed to a same memory element.
2. The memory controller of claim 1 , wherein the one or more near-memory processing commands for the first processor thread are at least partially interleaved with the one or more near-memory processing commands for the second processor thread when received by the memory controller.
3. The memory controller of claim 1 , wherein one or more bit values in the one or more near-memory processing commands are set based upon address information in the one or more near-memory processing commands.
4. The memory controller of claim 1 , wherein the one or more near-memory processing commands contains one or more command bit values.
5. The memory controller of claim 1 , further configured to issue the one or more near-memory processing commands for the second processor thread after all of the near-memory processing commands in a near-memory processing command sequence for the first processor thread have been issued.
6. The memory controller of claim 5 , further configured to identify a last near-memory processing command in the one or more near-memory processing commands for the first processor thread based upon one or more of: one or more bit values in the last near-memory processing command or a near-memory processing command that is designated as the last near-memory processing command for the first processor thread.
7. The memory controller of claim 1 , further configured to:
cause a data stored in a local storage of a near-memory processing element for the first processor thread to be stored to an other location,
upon completion of a near-memory processing command sequence for a third processor thread:
cause the data that was stored in the other location to be reloaded into the local storage of the near-memory processing element for the first processor thread, and
resume processing of the one or more near-memory processing commands for the first processor thread.
8. The memory controller of claim 1 , wherein said same memory element is one or more registers.
9. The memory controller of claim 1 , wherein the memory controller comprises one or more of a cache, a queue, or a buffer.
10. A processor comprising:
a first processor thread;
a second processor thread; and
a memory controller configured to:
issue one or more near-memory processing commands for a first processor thread; and
defer issuance of one or more near-memory processing commands for a second processor thread by performing one of:
moving the one or more near-memory processing commands for the second processor thread into deferred command storage, or
changing a pointer to skip the one or more near-memory processing commands for the second processor thread;
wherein the one or more near-memory processing commands for the first processor thread and the one or more near-memory processing commands for the second processor thread are directed to a same memory element.
11. The processor of claim 10 , wherein the one or more near-memory processing commands for the first processor thread are at least partially interleaved with the one or more near-memory processing commands for the second processor thread when received by the memory controller.
12. The processor of claim 10 , wherein one or more bit values in the one or more near-memory processing commands are set based upon address information in the one or more near-memory processing commands or are one or more command bit values.
13. The processor of claim 10 , wherein the memory controller is further configured to issue the one or more near-memory processing commands for the second processor thread after all of the near-memory processing commands in a near-memory processing command sequence for the first processor thread have been issued.
14. The processor of claim 13 , wherein the memory controller is further configured to identify a last near-memory processing command in the one or more near-memory processing commands for the first processor thread based upon one or more of:
one or more bit values in the last near-memory processing command or a near-memory processing command that is designated as the last near-memory processing command for the first processor thread.
15. The processor of claim 10 , wherein the memory controller is further configured to:
cause a data stored in a local storage of a near-memory processing element for the first processor thread to be stored to an other location,
upon completion of a near-memory processing command sequence for a third processor thread:
cause the data that was stored in the other location to be reloaded into the local storage of the near-memory processing element for the first processor thread, and
resume processing of the one or more near-memory processing commands for the first processor thread.
16. The processor of claim 10 , wherein the memory element is one or more registers.