Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method thereof, display device
A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.
1. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register; and
the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region;
the pixel array region comprises a first display region and a second display region, and the first display region and the second display region are juxtaposed to each other and do not overlap with each other, the first scan driving circuit is connected to the first display region to drive the first display region to display,
the display substrate further comprises a second scan driving circuit in the peripheral region and located on the first side of the base substrate, the second scan driving circuit and the first scan driving circuit are sequentially arranged along a scan direction of the pixel array region, and the second scan driving circuit is connected to the second display region to drive the second display region to display,
wherein the second scan driving circuit comprises a plurality of cascaded second shift registers,
the second signal line group further comprises a second trigger signal line configured to be connected to a first-stage second shift register of the plurality of cascaded second shift registers in the second scan driving circuit and to provide a second trigger signal to the first-stage second shift register in the second scan driving circuit;
the first trigger signal line comprises a part extending in an arrangement direction of the plurality of cascaded first shift registers, the second trigger signal line comprises a part extending in the arrangement direction of the plurality of cascaded first shift registers, an extension length of the part of the first trigger signal line and an extension length of the part of the second trigger signal line are identical to length of the first scan driving circuit and length of the second scan driving circuit.
2. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
both the plurality of power lines and the first signal line group are between the second signal line group and the pixel array region;
the plurality of power lines comprise a first power line and a second power line, and
the first power line and the second power line are configured to provide a same first power voltage.
3. The display substrate according to claim 2 , wherein the pixel array region comprises a first display region and a second display region, and the first display region and the second display region are juxtaposed to each other and do not overlap with each other, the first scan driving circuit is connected to the first display region to drive the first display region to display,
the display substrate further comprises a second scan driving circuit in the peripheral region and located on the first side of the base substrate, the second scan driving circuit and the first scan driving circuit are sequentially arranged along a scan direction of the pixel array region, and the second scan driving circuit is connected to the second display region to drive the second display region to display,
wherein the second scan driving circuit comprises a plurality of cascaded second shift registers,
the second signal line group further comprises a second trigger signal line configured to be connected to a first-stage second shift register of the plurality of cascaded second shift registers in the second scan driving circuit and to provide a second trigger signal to the first-stage second shift register in the second scan driving circuit.
4. The display substrate according to claim 3 , wherein the first trigger signal line and the second trigger signal line are juxtaposed.
5. The display substrate according to claim 3 , further comprising a fold line,
wherein an orthographic projection of the fold line on the base substrate is within an orthographic projection of the second display region on the base substrate, and the extending direction of the fold line is perpendicular to an extending direction of the first signal line group and an extending direction of the second signal line group.
6. The display substrate according to claim 3 , wherein each of the plurality of cascaded first shift registers of the first scan driving circuit comprises a first constituting transistor which is connected to the first power line and comprises a second constituting transistor and a third constituting transistor which are connected to the second power line,
an orthographic projection of the first constituting transistor on the base substrate is between an orthographic projection of the first signal line group on the base substrate and an orthographic projection of the first power line on the base substrate, and is close to the orthographic projection of the first power line on the base substrate,
an orthographic projection of the second constituting transistor on the base substrate and an orthographic projection of the third constituting transistor on the base substrate are between the orthographic projection of the first power line on the base substrate and an orthographic projection of the second power line on the base substrate, and is close to the orthographic projection of the second power line on the base substrate.
7. The display substrate according to claim 2 , wherein the plurality of power lines comprise a third power line and a fourth power line,
the third power line and the fourth power line are configured to provide a same second power voltage;
an orthographic projection of the fourth power line on the base substrate partially overlaps with an orthographic portion of the first scan driving circuit on the base substrate;
an orthographic projection of the third power line on the base substrate is between the orthographic projection of the fourth power line on the base substrate and an orthographic projection of the first signal line group on the base substrate.
8. The display substrate according to claim 7 , wherein each of the plurality of cascaded first shift registers of the first scan driving circuit further comprises a fourth constituting transistor connected to the third power line and a fifth constituting transistor connected to the fourth power line,
an orthographic projection of the fourth constituting transistor on the base substrate is on a side, away from the orthographic projection of the first signal line group on the base substrate, of the orthographic projection of the third power line on the base substrate, and is close to the orthographic projection of the third power line on the base substrate,
an orthographic projection of the fifth constituting transistor on the base substrate is between the orthographic projection of the fourth power line on the base substrate and an orthographic projection of the second signal line group on the base substrate, and is close to the orthographic projection of the fourth power line on the base substrate.
9. The display substrate according to claim 2 , wherein the first scan driving circuit comprises a first transistor, a second transistor, and a third transistor, and the first transistor, the second transistor, and the third transistor are respectively connected to the first signal line group,
an extending direction of a channel of the first transistor, an extending direction of a channel of the second transistor, and an extending direction of a channel of the third transistor are parallel to an extending direction of the first signal line group and an extending direction of the second signal line group.
10. The display substrate according to claim 9 , wherein the first scan driving circuit further comprises a sixth transistor and a seventh transistor, and the sixth transistor and the seventh transistor are respectively connected to the first signal line group,
an extending direction of a channel of the sixth transistor and an extending direction of a channel of the seventh transistor are parallel to the extending direction of the first signal line group and the extending direction of the second signal line group.
11. A display device, comprising the display substrate according to claim 2 .
12. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region; and
a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
both the plurality of power lines and the first signal line group are between the second signal line group and the pixel array region;
the plurality of power lines comprise a first power line and a second power line,
the first power line and the second power line are configured to provide a same first power voltage;
an orthographic projection of the first power line on the base substrate partially overlaps with an orthographic projection of the first scan driving circuit on the base substrate; and
an orthographic projection of the second power line on the base substrate is between the orthographic projection of the first power line on the base substrate and an orthographic projection of the second signal line group on the base substrate.