Compute-in-memory cell
A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.
1 . A device, comprising:
a first memory cell configured to store a first bit at a first node;
a second memory cell configured to store a second bit at a second node;
a logic element configured to perform logic functions of:
a first logic element configured to perform an OR function and including a first node input terminal connected to the first node, a first read word line input terminal connected to a first read word line, and a first output terminal;
a second logic element configured to perform an OR function and including a second node input terminal connected to the second node, a second read word line input terminal connected to a second read word line, and a second output terminal; and
a third logic element configured to perform a NAND function and including a first input terminal connected to the first output terminal of the first logic element and a second input terminal connected to the second output terminal of the second logic element, wherein the first input terminal and the second input terminal are at different nodes.
2 . The device of claim 1 , wherein the first memory cell includes a latch.
3 . The device of claim 1 , wherein the first memory cell includes a capacitor.
4 . The device of claim 1 , wherein the logic element consists essentially of eight metal-oxide semiconductor field-effect transistors and interconnections between at least some of the eight metal-oxide semiconductor field-effect transistors.
5 . The device of claim 1 , comprising:
a third memory cell configured to store a third bit at a third node; and
the logic element is configured to perform logic functions of a fourth logic element including a third node input terminal coupled to the third node,
wherein the third logic element includes a third input terminal coupled to a third output terminal of the fourth logic element.
6 . The device of claim 5 , wherein the logic element consists essentially of twelve metal-oxide semiconductor field-effect transistors and interconnections between at least some of the twelve metal oxide semiconductor field effect transistors.
7 . The device of claim 1 , comprising:
a third memory cell configured to store a third bit at a third node;
a fourth memory cell configured to store a fourth bit at a fourth node;
the logic element configured to perform logic functions of:
a fourth logic element including a third node input terminal coupled to the third node;
a fifth logic element including a fourth node input terminal coupled to the fourth node;
a sixth logic element including a third input terminal coupled to a third output terminal of the fourth logic element and a fourth input terminal coupled to a fourth output terminal of the fifth logic element; and
a seventh logic element including a first logic input terminal coupled to a first logic output terminal of the third logic element and a second logic input terminal coupled to a second logic output terminal of the sixth logic element.
8 . The device of claim 1 , wherein the logic element consists essentially of eight metal-oxide semiconductor field-effect transistors and interconnections between at least some of the eight metal-oxide semiconductor field-effect transistors, wherein only two of the eight metal-oxide semiconductor field-effect transistors have drain/source paths directly connected to a power source.
9 . The device of claim 1 , wherein the logic element consists essentially of eight metal-oxide semiconductor field-effect transistors and interconnections between at least some of the eight metal-oxide semiconductor field-effect transistors, wherein four of the eight metal-oxide semiconductor field-effect transistors are N-channel metal-oxide semiconductor field-effect transistors and four of the eight metal-oxide semiconductor field-effect transistors are P-channel metal-oxide semiconductor field-effect transistors.
10 . The device of claim 9 , wherein in a first series of transistors two of the P-channel metal-oxide semiconductor field-effect transistors are connected in series to two of the N-channel metal-oxide semiconductor field-effect transistors, and in a second series of transistors another two of the P-channel metal-oxide semiconductor field-effect transistors are connected in series to another two of the N-channel metal-oxide semiconductor field-effect transistors.
11 . A device, comprising:
a select circuit configured to receive read select signals and an input signal and provide read word line output signals on a first read word line and a second read word line based on the read select signals and the input signal;
a memory circuit including:
a first memory cell configured to store a first bit at a first node; and
a second memory cell configured to store a second bit at a second node; and
a multiply circuit configured to receive the read word line output signals, the first bit, and the second bit and provide a multiplication result,
the multiply circuit configured to perform logic functions of:
a first logic element configured to perform an OR function and including a first node input terminal connected to the first node, a first read word line input terminal connected to the first read word line, and a first output terminal;
a second logic element configured to perform an OR function and including a second mode input terminal connected to the second node, a second read word line input terminal connected to the second read word line, and a second output terminal; and
a third logic element configured to perform a NAND function and including a first input terminal connected to the first output terminal of the first logic element and a second input terminal connected to the second output terminal of the second logic element, wherein the first input terminal and the second input terminal are different nodes.
12 . The device of claim 11 , wherein the select circuit includes:
a first select logic element configured to receive one of the read select signals and the input signal and provide one of the read word line output signals; and
a second select logic element configured to receive another one of the read select signals and the input signal and provide another one of the read word line output signals.
13 . The device of claim 11 , wherein the multiply circuit consists essentially of eight metal-oxide semiconductor field-effect transistors and interconnections between at least some of the eight metal-oxide semiconductor field-effect transistors.
14 . The device of claim 11 , wherein the first memory cell includes a latch that includes six or more metal-oxide semiconductor field-effect transistors.
15 . The device of claim 11 , wherein the multiply circuit consists essentially of eight metal-oxide semiconductor field-effect transistors and interconnections between at least some of the eight metal-oxide semiconductor field-effect transistors, wherein four of the eight metal-oxide semiconductor field-effect transistors are N-channel metal-oxide semiconductor field-effect transistors and four of the eight metal-oxide semiconductor field-effect transistors are P-channel metal-oxide semiconductor field-effect transistors.
16 . The device of claim 15 , wherein in a first series of transistors two of the P-channel metal-oxide semiconductor field-effect transistors are connected in series to two of the N-channel metal-oxide semiconductor field-effect transistors, and in a second series of transistors another two of the P-channel metal-oxide semiconductor field-effect transistors are connected in series to another two of the N-channel metal-oxide semiconductor field-effect transistors.
17 . A method of multiplying in an integrated circuit memory, comprising:
storing a first bit at a first node in a first memory cell;
storing a second bit at a second node in a second memory cell;
receiving read select signals and an input signal at a select circuit;
outputting, by the select circuit, read word line output signals based on the read select signals and the input signal;
receiving the read word line output signals, the first bit, and the second bit at a multiply circuit;
and
outputting, by the multiply circuit, a multiplication result
wherein receiving the read word line output signals, the first bit, and the second bit at a multiply circuit includes:
receiving one of the read word line output signals and the first bit at a first logic element configured to perform an OR function and including a first output terminal:
receiving another one of the read word line output signals and the second bit at a second logic element configured to perform an OR function and including a second output terminal:
receiving a first output from the first output terminal of the first logic element at a first input terminal of a third logic element configured to perform a NAND function; and
receiving a second output from the second output terminal of the second logic element at a second input terminal of the third logic element, wherein the first input terminal and the second input terminal are different nodes.
18 . The method of claim 17 , wherein receiving read select signals and an input signal at a select circuit includes:
receiving one of the read select signals and the input signal at a first select logic element; and
receiving another one of the read select signals and the input signal at a second select logic element.
19 . The method of claim 17 , wherein outputting, by the select circuit, read word line output signals based on the read select signals and the input signal includes:
outputting, by a first select logic element, one of the read word line output signals; and
outputting, by a second select logic element, another one of the read word line output signals.
20 . The method of claim 17 , comprising:
outputting the multiplication result based on the first output and the second output from the third logic element.