Insulated gate bipolar transistor (IGBT) semiconductor device with reduced turn-on loss
S 1 ≤S 2 <S 3 being satisfied, where S 1 is a surface area of the first gate electrode and the third semiconductor layer facing each other via the first insulating film, S 2 is a surface area of the second gate electrode and the third semiconductor layer facing each other via the second insulating film, and S 3 is a surface area of the third gate electrode and the third semiconductor layer facing each other via the third insulating film.
1 . A semiconductor device, comprising:
a first electrode;
a second electrode;
a semiconductor part located between the first electrode and the second electrode, the semiconductor part including
a first semiconductor layer of a first conductivity type,
a second semiconductor layer of a second conductivity type,
a third semiconductor layer of the first conductivity type,
a fourth semiconductor layer of the second conductivity type, and
a fifth semiconductor layer of the second conductivity type;
a group of gate electrodes located between the semiconductor part and the first electrode, the group of gate electrodes including one or more first gate electrodes, one or more second gate electrodes, and one or more third gate electrodes, each of the first to third gate electrodes in the group facing the first to third semiconductor layers and the first to third gate electrodes in the group being electrically isolated from each other;
a first insulating film located between each of the one or more first gate electrodes and the semiconductor part;
a second insulating film located between each of the one or more second gate electrodes and the semiconductor part; and
a third insulating film located between each of the one or more third gate electrodes and the semiconductor part,
the second semiconductor layer being located between the first semiconductor layer and the third semiconductor layer,
the third semiconductor layer being located between the second semiconductor layer and the first electrode and electrically connected to the first electrode,
the fourth semiconductor layer being located between the first semiconductor layer and the second electrode and electrically connected to the second electrode,
the fifth semiconductor layer being located between the second semiconductor layer and the first electrode and electrically connected to the first electrode, the fifth semiconductor layer having a higher second-conductivity-type impurity concentration than the second semiconductor layer,
the third semiconductor layer and the fifth semiconductor layer being alternately arranged in a direction in which the first to third gate electrodes extend,
S1≤S2<S3 being satisfied, where S1 is a total surface area of the one or more first gate electrodes and the third semiconductor layer facing each other via the first insulating film, S2 is a total surface area of the one or more second gate electrodes and the third semiconductor layer facing each other via the second insulating film, and S3 is a total surface area of the one or more third gate electrodes and the third semiconductor layer facing each other via the third insulating film.
2 . The device according to claim 1 , wherein
a number of the one or more third gate electrodes is greater than a number of the one or more second gate electrodes, and
the number of the one or more second gate electrodes is not less than a number of the one or more first gate electrodes.
3 . The device according to claim 1 , wherein
the first electrode includes a trench contact part extending through the third semiconductor layer and contacting the fifth semiconductor layer.
4 . The device according to claim 1 , wherein
the semiconductor part further includes a sixth semiconductor layer of the first conductivity type,
the sixth semiconductor layer is located between the fourth semiconductor layer and the first semiconductor layer, and
the sixth semiconductor layer has a higher first-conductivity-type impurity concentration than the first semiconductor layer.
5 . The device according to claim 1 , wherein
the first electrode and the second electrode are separated from each other in a first direction,
the semiconductor part includes a plurality of mesa parts separated from each other in a second direction orthogonal to the first direction,
each of the mesa parts extends in a third direction and includes the third semiconductor layer, the second semiconductor layer, and a portion of the first semiconductor layer, and
the third direction is orthogonal to the first and second directions.
6 . The device according to claim 5 , wherein
volume ratios of the third semiconductor layers are different between the mesa parts next to each other in the second direction.
7 . The device according to claim 5 , wherein
the mesa part further includes the fifth semiconductor layer of the second conductivity type, and
the third semiconductor layer and the fifth semiconductor layer are alternately arranged in the third direction.
8 . The device according to claim 1 , wherein
a potential of the first gate electrode, a potential of the second gate electrode, and a potential of the third gate electrode are controlled independently from each other.
9 . The device according to claim 8 , wherein
a first control potential applied to the first gate electrode at a first timing is greater than a first threshold voltage of the first gate electrode,
a second control potential applied to the second gate electrode at a second timing is greater than a second threshold voltage of the second gate electrode,
a third control potential applied to the third gate electrode at a third timing is greater than a third threshold voltage of the third gate electrode,
the third control potential is set to be less than the third threshold voltage at a fourth timing after the first to third timings,
the second control potential is set to be less than the second threshold voltage at a fifth timing after the fourth timing, and
the first control potential is set to be less than the first threshold voltage at a sixth timing after the fifth timing.
10 . The device according to claim 9 , wherein
the first timing, the second timing, and the third timing are simultaneous.
11 . The device according to claim 9 , wherein
a period between the second timing and the fifth timing is greater than a period between the fifth timing and the sixth timing.
12 . The device according to claim 9 , wherein
a period between the fourth timing and the fifth timing is greater than a period between the fifth timing and the sixth timing.
13 . The device according to claim 1 , comprising:
an IGBT (Insulated Gate Bipolar Transistor).
14 . The device according to claim 1 , wherein
the first conductivity type is an n-type, and
the second conductivity type is a p-type.