IP Library Granted Patent US 12,484,255
Granted Patent B2
US 12,484,255 · App. 17/859,004 · Granted Nov 25, 2025

Semiconductor device

Inventors: Takeshi Sakai (Tokyo, JP); Hajime Watakabe (Tokyo, JP); Akihiro Hanada (Tokyo, JP)
Assignee: Magnolia White Corporation
H10D30/6755H10D30/6734H10D86/423H10D86/441H10D86/471H10D86/60
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Quick Facts
Patent No.
US 12,484,255
App. No.
17/859,004
Granted
Nov 25, 2025
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a first transistor which includes a an oxide semiconductor layer, and a second transistor connected to first and a second gate electrodes of the first transistor, wherein the oxide semiconductor layer is provided between the first and second gate electrodes in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view, and a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.

Claims (40)

1 . A semiconductor device comprising:

a first transistor comprising:

a first gate electrode;

an oxide semiconductor layer overlapping the first gate electrode;

a source electrode and a drain electrode each overlapping the oxide semiconductor layer; and

a second gate electrode overlapping a central portion of the oxide semiconductor layer;

a second transistor connected to the first gate electrode and the second gate electrode; and

a metal wiring line provided between the second gate electrode and the second transistor, wherein

the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view,

the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view,

a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor, and

the metal wiring has a higher resistance value than that of a wiring line provided between the first gate electrode and the second transistor.

2 . The semiconductor device according to claim 1 , wherein

the second transistor is a thin-film transistor of which a channel formation region is formed from a silicon layer.

3 . A semiconductor device comprising:

a first transistor comprising:

a first gate electrode;

an oxide semiconductor layer overlapping the first gate electrode;

a source electrode and a drain electrode each overlapping the oxide semiconductor layer;

a second gate electrode overlapping a central portion of the oxide semiconductor layer;

a second transistor connected to the first gate electrode and the second gate electrode; and

a metal wiring line provided between the second gate electrode and the second transistor, wherein

the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view,

the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view,

a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor, and

the metal wiring line has a less width and than that of a wiring line provided between the first gate electrode and the second transistor.

4 . The semiconductor device according to claim 3 , wherein

the second transistor is a thin-film transistor of which a channel formation region is formed from a silicon layer.

5 . A semiconductor device comprising:

a first transistor comprising:

a first gate electrode;

an oxide semiconductor layer overlapping the first gate electrode;

a source electrode and a drain electrode each overlapping the oxide semiconductor layer; and

a second gate electrode overlapping a central portion of the oxide semiconductor layer;

a second transistor connected to the first gate electrode and the second gate electrode; and

a third transistor connected to the second gate electrode, wherein

the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view,

the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view,

a threshold value of the third transistor is higher than a threshold value of the second transistor, and

the second transistor and the third transistor are each a thin-film transistor of which a channel formation region is formed from a silicon layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071741/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2022
From: SAKAI, TAKESHI; WATAKABE, HAJIME; HANADA, AKIHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 060429/0124 →
Priority Claims (1)
JP 2021-113653 · Jul 8, 2021 · national
Continuity (1)
Related Publication 20230007861A1 · Jan 12, 2023
References Cited (9)
US 20130299819A1 · Yamazaki et al. · 2013 [cited by applicant]
US 20190035818A1 · Yamazaki · 2019 [cited by examiner]
US 20200020756A1 · Ueda · 2020 [cited by examiner]
US 20200259020A1 · Watakabe et al. · 2020 [cited by applicant]
US 20210151475A1 · Kim · 2021 [cited by examiner]
JP 2013254950A · 2013 [cited by applicant]
JP 2020129635A · 2020 [cited by applicant]
JP 2021100123A · 2021 [cited by applicant]
Office Action issued Jan. 28, 2025, in corresponding JP Application No. 2021-113653, 6pp. [cited by applicant]