IP Library › Granted Patent US 12,040,976
Granted Patent B2
US 12,040,976 · App. 17/859,722 · Granted Jul 16, 2024

Packet header field extraction

Inventor: Patrick Bosshart (Plano, TX)
Assignee: BAREFOOT NETWORKS, INC
H04L45/74591H04L45/54H04L45/64H04L45/72H04L49/101H04L49/1546H04L69/22H04L45/38H04L45/42H04L45/74
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Quick Facts
Patent No.
US 12,040,976
App. No.
17/859,722
Granted
Jul 16, 2024
Kind
B2
Abstract

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

Claims (140)

1. At least one non-transitory machine readable medium storing program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline for use in association with a network switch, the network switch comprising hardware, the at least one packet processing pipeline comprising at least one parser stage, at least one match-action stage, and at least one other stage, the network switch, when in operation, being to receive at least one ingress packet, the at least one packet processing pipeline being to process the at least one ingress packet to generate at least one egress packet for being output via the network switch, the program instructions, when executed by the at least one machine, resulting in the at least one machine being configured for performing operations comprising:

generating the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code describing, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

wherein:

when the network switch is in the operation, the network switch is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively;

the network switch is configurable for use with both ternary content addressable memory (TCAM) and other memory;

the TCAM and the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate GRE and/or GENEVE tunneling encapsulation-related operations; and

the at least one other stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

2. The at least one non-transitory machine readable medium of claim 1 , wherein:

the operations further comprise compiling the programming language code to produce the compilation;

the at least one other stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

3. The at least one non-transitory machine readable medium of claim 2 , wherein:

a chip comprises the network switch; and

the configuration data defines, at least in part, the match-action table data.

4. The at least one non-transitory machine readable medium of claim 3 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

5. A method implemented, at least in part, using program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline for use in association with a network switch, the network switch comprising hardware, the at least one packet processing pipeline comprising at least one parser stage, at least one match-action stage, and at least one other stage, the network switch, when in operation, being to receive at least one ingress packet, the at least one packet processing pipeline being to process the at least one ingress packet to generate at least one egress packet for being output via the network switch, the method comprising:

executing, by the at least one machine, the program instructions, the program instructions, when executed by the at least one machine, permitting generation of the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code describing, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

wherein:

when the network switch is in the operation, the network switch is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively;

the network switch is configurable for use with both ternary content addressable memory (TCAM) and other memory;

the TCAM and the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate GRE and/or GENEVE tunneling encapsulation-related operations; and

the at least one other stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

6. The method of claim 5 , wherein:

the method further comprises compiling the programming language code to produce the compilation;

the at least one other stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

7. The method of claim 6 , wherein:

a chip comprises the network switch; and

the configuration data defines, at least in part, the match-action table data.

8. The method of claim 7 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

9. At least one packet processing pipeline for use in association with a network switch, the network switch comprising hardware, the network switch, when in operation, being to receive at least one ingress packet, the at least one packet processing pipeline comprising:

at least one parser stage;

at least one match-action stage; and

at least one other stage;

wherein:

the at least one packet processing pipeline is programmable, at least in part, via configuration data;

the at least one packet processing pipeline is to process the at least one ingress packet to generate at least one egress packet for being output via the network switch;

the configuration data is to be generated based upon compilation of programming language code;

the programming language code is user-generated, at least in part;

the programming language code is to describe, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

when the network switch is in the operation, the network switch is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively;

the network switch is configurable for use with both ternary content addressable memory (TCAM) and other memory;

the TCAM and the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate GRE and/or GENEVE tunneling encapsulation-related operations; and

the at least one other stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

10. The at least one packet processing pipeline of claim 9 , wherein:

the programming language code is to be compiled to produce the compilation;

the at least one other stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

11. The at least one packet processing pipeline of claim 10 , wherein:

a chip comprises the network switch; and

the configuration data defines, at least in part, the match-action table data.

12. The at least one packet processing pipeline of claim 11 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

13. At least one non-transitory machine readable medium storing program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline comprised in network switch circuitry, the at least one packet processing pipeline comprising at least one parser stage, at least one match-action stage, and at least one deparser stage, the network switch circuitry, when in operation, to receive at least one ingress packet, the at least one packet processing pipeline to process the at least one ingress packet to generate at least one egress packet for being output via the network switch circuitry, the program instructions, when executed by the at least one machine, resulting in the at least one machine being configured for performing operations comprising:

generating the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code describing, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

wherein:

when the network switch circuitry is in the operation, the network switch circuitry is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match-action stage and the at least one deparser stage, respectively;

the network switch circuitry is to use both ternary content addressable memory (TCAM) and other memory;

the TCAM and/or the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate tunneling encapsulation-related operations; and

the at least one deparser stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

14. The at least one non-transitory machine readable medium of claim 13 , wherein:

the operations further comprise compiling the programming language code to produce the compilation;

the at least one deparser stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

15. The at least one non-transitory machine readable medium of claim 14 , wherein:

a chip comprises the network switch circuitry; and

the configuration data defines, at least in part, the match-action table data.

16. The at least one non-transitory machine readable medium of claim 15 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

17. A method implemented, at least in part, using program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline comprised in network switch circuitry, the at least one packet processing pipeline comprising at least one parser stage, at least one match-action stage, and at least one deparser stage, the network switch circuitry, when in operation, to receive at least one ingress packet, the at least one packet processing pipeline to process the at least one ingress packet to generate at least one egress packet for being output via the network switch circuitry, the method comprising:

executing, by the at least one machine, the program instructions, the program instructions, when executed by the at least one machine, permitting generation of the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code describing, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

wherein:

when the network switch circuitry is in the operation, the network switch circuitry is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match- action stage and the at least one deparser stage, respectively;

the network switch circuitry is to use both ternary content addressable memory (TCAM) and other memory;

the TCAM and/or the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate tunneling encapsulation-related operations; and

the at least one deparser stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

18. The method of claim 17 , wherein:

the method further comprises compiling the programming language code to produce the compilation;

the at least one deparser stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

19. The method of claim 18 , wherein:

a chip comprises the network switch circuitry; and

the configuration data defines, at least in part, the match-action table data.

20. The method of claim 19 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

21. At least one packet processing pipeline comprised in network switch circuitry, the network switch circuitry, when in operation, to receive at least one ingress packet, the at least one packet processing pipeline comprising:

at least one parser stage;

at least one match-action stage; and

at least one deparser stage;

wherein:

the at least one packet processing pipeline is to be programmed, at least in part, using configuration data;

the at least one packet processing pipeline is to process the at least one ingress packet to generate at least one egress packet for being output via the network switch circuitry;

the configuration data is to be generated based upon compilation of programming language code;

the programming language code is to be user-generated, at least in part;

the programming language code is to describe, at least in part:

header field parsing, by the at least one parser stage, of the at least one ingress packet; and

header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the at least one ingress packet;

when the network switch circuitry is in the operation, the network switch circuitry is to associate respective subsets of header fields of the at least one ingress packet with each other in respective sets of memory locations;

the respective sets of memory locations are for use by the at least one match-action stage and the at least one deparser stage, respectively;

the network switch circuitry is to use both ternary content addressable memory (TCAM) and other memory;

the TCAM and/or the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part;

the match-action table data is configurable, based upon the configuration data, to indicate tunneling encapsulation-related operations; and

the at least one deparser stage is to generate, at least in part, the at least one egress packet based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying.

22. The at least one packet processing pipeline of claim 21 , wherein:

the programming language code is be compiled to produce the compilation;

the at least one deparser stage is to generate, at least in part, the at least one egress packet; and

the at least one match-action stage comprises a plurality of match-action stages.

23. The at least one packet processing pipeline of claim 22 , wherein:

a chip comprises the network switch circuitry; and

the configuration data defines, at least in part, the match-action table data.

24. The at least one packet processing pipeline of claim 23 , wherein:

the at least one ingress packet comprises packet headers; and

the programming language code describes, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, the packet headers and (2) to identify from the packet headers the respective subsets of header fields.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2026
From: BAREFOOT NETWORKS, INC.
To: INTEL CORPORATION
Reel/Frame 075834/0019 →
Continuity (5)
Continuation 16695049 · Nov 25, 2019
Continuation 16573847 · Sep 17, 2019
Continuation 15729555 · Oct 10, 2017
Continuation 14836850 · Aug 26, 2015
Related Publication 20220345405A1 · Oct 27, 2022