IP Library › Granted Patent US 12,046,683
Granted Patent B2
US 12,046,683 · App. 17/861,432 · Granted Jul 23, 2024

Semiconductor device

Inventors: Yutaka Okazaki (Kanagawa, JP); Akihisa Shimomura (Kanagawa, JP); Naoto Yamade (Kanagawa, JP); Tomoya Takeshita (Kanagawa, JP); Tetsuhiro Tanaka (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78696H01L27/1225H01L27/1255H01L29/45H01L29/4908H01L29/66969H01L29/78609H01L29/78648H01L29/7869
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Quick Facts
Patent No.
US 12,046,683
App. No.
17/861,432
Granted
Jul 23, 2024
Kind
B2
Abstract

A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

Claims (31)

1. A semiconductor device comprising:

an inverter including a first transistor and a second transistor,

wherein the first transistor includes a first channel formation region comprising silicon, and a first gate electrode over the first channel formation region,

wherein the second transistor includes a second channel formation region comprising oxide semiconductor, and a second gate electrode over the second channel formation region,

wherein a first insulator is provided over the first gate electrode,

wherein a second insulator is provided over the second gate electrode,

wherein a first conductor and a second conductor are provided over the second insulator,

wherein the second channel formation region is located over the first insulator,

wherein the first gate electrode is electrically connected to the second gate electrode through the first conductor,

wherein the first conductor has a region in contact with a top surface of the second insulator,

wherein the first insulator has a region in contact with a top surface of the first gate electrode, and has an opening for electrically connecting the first gate electrode and the first conductor,

wherein the opening is provided in a region not overlapping the first channel formation region, and

wherein the second conductor has a region in contact with a top surface of the second insulator, and is electrically connected to one of a source and a drain of the first transistor, and to one of a source and a drain of the second transistor. wherein the insulator is located over the second gate electrode.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor includes indium, gallium and zinc.

3. A semiconductor device comprising:

an inverter including a first transistor and a second transistor,

wherein the first transistor includes a first channel formation region comprising silicon, and a first gate electrode over the first channel formation region,

wherein the second transistor includes a second channel formation region comprising oxide semiconductor, a second gate electrode over the second channel formation region, and a third gate electrode below the second channel formation region,

wherein a first insulator is provided over the first gate electrode,

wherein a second insulator is provided over the second gate electrode,

wherein a first conductor and a second conductor are provided over the second insulator,

wherein the second gate electrode is electrically connected to the third gate electrode,

wherein the second channel formation region is located over the first insulator,

wherein the first gate electrode is electrically connected to the second gate electrode through the first conductor,

wherein the first conductor has a region in contact with a top surface of the second insulator,

wherein the first insulator has a region in contact with a top surface of the first gate electrode, and has an opening for electrically connecting the first gate electrode and the first conductor,

wherein the opening is provided in a region not overlapping the first channel formation region, and

wherein the second conductor has a region in contact with a top surface of the second insulator, and is electrically connected to one of a source and a drain of the first transistor, and to one of a source and a drain of the second transistor.

4. The semiconductor device according to claim 3 , wherein the oxide semiconductor includes indium, gallium and zinc.

5. The semiconductor device according to claim 1 , wherein the first conductor has a region overlapping a third conductor configured to be the first gate electrode, and a fourth conductor configured to be the second gate electrode.

6. The semiconductor device according to claim 3 , wherein the first conductor has a region overlapping a third conductor configured to be the first gate electrode, and a fourth conductor configured to be the second gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2022
From: OKAZAKI, YUTAKA; SHIMOMURA, AKIHISA; YAMADE, NAOTO; TAKESHITA, TOMOYA; TANAKA, TETSUHIRO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 060470/0783 →
Priority Claims (1)
JP 2015-140794 · Jul 14, 2015 · national
Continuity (4)
Continuation 17006987 · Aug 31, 2020
Continuation 16367329 · Mar 28, 2019
Continuation 15204015 · Jul 7, 2016
Related Publication 20220352387A1 · Nov 3, 2022