Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns

1. A non-transitory machine-readable medium having machine-readable instructions, the machine-readable instructions comprising:

an integrated circuit (IC) test engine that generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design, where N is an integer greater than or equal to two; and

a diagnostics engine that:

receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by automatic test equipment (ATE), in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;

employs a fault simulator to:

fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects; and

fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with test patterns that have one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns; and

scores candidate fault and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

2. The medium of claim 1 , wherein the sim-shifting of the subset of the N-cycle at-speed test patterns comprises:

fault-simulating a scan-in shift interval of a respective N-cycle at-speed test pattern of the subset of the N-cycle at-speed test patterns to identify a set of values prior to a fault initialization cycle of the respective N-cycle at-speed test pattern; and

employing the set of values prior to the fault initialization cycle during the scan-in shift interval of the respective N-cycle at-speed test pattern as extra fault initialization cycles for a corresponding N+P cycle at-speed test pattern, where P is a positive integer to diagnose a respective transition fault and/or defect of the second set of transition faults and/or defects.

3. The medium of claim 2 , wherein the scoring comprises comparing the test result data and fault simulation results for the faults and/or defects in a combination of the first set and the second set of transition faults and/or defects to determine an order of probability that the set of miscompare values of the test result data for the given N-cycle at-speed test pattern are caused by a given transition fault and/or defect and other transition faults and/or defects.

4. The medium of claim 3 , wherein each candidate fault and/or defect in the second set of transition faults and/or defects is a multicycle transition cell-aware candidate defect.

5. The medium of claim 4 , wherein each candidate fault and/or defect in the first set of transition faults and/or defects is a multicycle transition fault and/or defect.

6. The medium of claim 3 , wherein the test result data and fault simulation results for a given fault/defect are aggregated across one or more measures in a given N-cycle at-speed test pattern.

7. The medium of claim 6 , wherein the diagnostics engine determines that a probability of the set of miscompare values being caused by the transition fault and/or defect of the second set of transition faults and/or defects is greater than the probability of the set of miscompare values being caused by a transition fault and/or defect of the first set of transition faults and/or defects.

8. The medium of claim 6 , wherein the probability associated with a presence of a fault/defect on a fabricated IC chip is based on an aggregation of comparisons between the fault simulation results and the test result data for two or more N-cycle at-speed test patterns.

9. The medium of claim 8 , wherein the comparison aggregates the fault simulation results and the test result data for two or more faults and/or defects from the subset of the N-cycle at-speed test patterns.

10. The medium of claim 6 , wherein the probability for a particular candidate fault and/or defect is increased or decreased based on a respective consistency or inconsistency between the test result data and fault-simulation of the particular candidate fault and/or defect.

11. A system comprising:

automatic test equipment (ATE) that applies N-cycle at-speed test patterns to a fabricated integrated circuit (IC) chip that is based on an IC design and provides test result data characterizing application of the N-cycle at-speed test patterns to the fabricated IC chip, where N is an integer greater than or equal to two, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;

a non-transitory memory that stores machine-readable instructions; and

a processing unit that accesses the memory and executes the machine-readable instructions, the machine-readable instructions comprising:

an IC test engine that generates the N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of the IC design; and

a diagnostics engine that:

employs a fault simulator to fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with a multicycle test pattern having one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns; and

scores candidate faults and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the subset of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

12. The system of claim 11 , wherein the sim-shifting of the subset of the N-cycle at-speed test patterns comprises:

fault-simulating a scan-in shift interval of a respective N-cycle at-speed test pattern of the subset of the N-cycle at-speed test patterns to identify a set of values prior to a fault initialization cycle of the respective N-cycle at-speed test pattern; and

employing the set of values prior to the fault initialization cycle during the scan-in shift interval of the respective N-cycle at-speed test pattern as extra fault initialization cycles for a corresponding N+P cycle at-speed test pattern, where P is a positive integer to diagnose a respective transition fault and/or defect of the second set of transition faults and/or defects.

13. The system of claim 12 , wherein the scoring comprises comparing the test result data and fault simulation results for the transition faults and/or defects in a combination of the first set and second set of transition faults and/or defects to determine an order of probability that the set of miscompare values of the test results for the given N-cycle at-speed test pattern are caused by a given transition fault and/or defect and other transition faults and/or defects.

14. The system of claim 13 , wherein the probability associated with the set of miscompare values is based on a comparison of the test result data and fault simulation results for a set of faults and/or defects against the given test pattern of the subset of the N-cycle at-speed test patterns.

15. The system of claim 13 , wherein the diagnostics engine determines that probability of the set of miscompare values being caused by a transition fault and/or defect of the second set of transition faults and/or defects is greater than the probability of the set of miscompare values being caused by a transition fault and/or defect of the first set of transition faults and/or defects.

16. The system of claim 15 , wherein the transition fault and/or defect of the second set of transition faults and/or defects is an open wire defect in the fabricated IC chip.

17. The system of claim 13 , wherein the comparing aggregates the fault simulation results and the test result data for two or more measures from a given N-cycle at-speed test pattern of the subset of the N-cycle at-speed test patterns.

18. A method for diagnosing faults and/or defects in a fabricated integrated circuit (IC) chip, the method comprising:

generating, by an IC test engine operating on a computing platform, N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design, where N is an integer greater than or equal to two;

applying, by automatic test equipment (ATE) the N-cycle at-speed test patterns to a fabricated IC chip that is based on the IC design and provides test result data characterizing application of the N-cycle at-speed test patterns to the fabricated IC chip, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;

selectively fault-simulating, by a fault simulator of a diagnostics engine operating on the computing platform, a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns having one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns; and

scoring, by the diagnostics engine candidate, faults and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the subset of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

19. The method of claim 18 , wherein the sim-shifting of the subset of the N-cycle at-speed test patterns comprises:

fault-simulating a scan-in shift interval of a respective N-cycle at-speed test pattern of the subset of the N-cycle at-speed test patterns to identify a set of values prior to a fault initialization cycle of the respective N-cycle at-speed test pattern; and

employing the set of values prior to the fault initialization cycle during the scan-in shift interval of the respective N-cycle at-speed test pattern as extra fault initialization cycles for a corresponding N+P cycle at-speed test pattern, where P is a positive integer to diagnose a respective transition fault and/or defect of the second set of transition faults and/or defects.

20. The method of claim 18 , wherein the scoring comprises comparing the test result data and fault simulation results for the faults and/or defects in a combination of the first set and the second set of transition faults and/or defects to determine an order of probability that the set of miscompare values of the test results for the given N-cycle at-speed test pattern are caused by a given transition fault and/or defect and other transition faults and/or defects.