Embedded ferroelectric memory cell

1. An integrated chip structure, comprising:

a first source/drain region and a second source/drain region disposed within a substrate;

a select gate disposed over the substrate between the first source/drain region and the second source/drain region;

a ferroelectric random-access memory (FeRAM) device disposed over the substrate between the select gate and the first source/drain region;

a first sidewall spacer comprising one or more dielectric materials arranged laterally between the select gate and the FeRAM device; and

an inter-level dielectric (ILD) structure laterally surrounding the FeRAM device and the select gate and vertically overlying a top surface of the first sidewall spacer.

2. The integrated chip structure of claim 1 , wherein the select gate has a first maximum width and the FeRAM device has a second maximum width that is greater than the first maximum width.

3. The integrated chip structure of claim 1 , wherein the FeRAM device comprises:

a ferroelectric material disposed over a dielectric layer; and

a conductive electrode disposed over the ferroelectric material.

4. The integrated chip structure of claim 3 , wherein the dielectric layer continuously extends from directly below the conductive electrode to directly below the select gate.

5. The integrated chip structure of claim 1 , further comprising:

a boundary isolation structure disposed within the substrate between a memory region of the substrate comprising the FeRAM device and a logic region of the substrate comprising a transistor device.

6. The integrated chip structure of claim 5 , further comprising:

one or more shallow trench isolation (STI) structures disposed within the memory region, wherein the boundary isolation structure continuously extends for a greater width than respective ones of the one or more STI structures along a cross-sectional view.

7. The integrated chip structure of claim 5 , wherein a sidewall of the boundary isolation structure protrudes outward from within the substrate to over an upper surface of the substrate.

8. The integrated chip structure of claim 5 , further comprising:

a boundary dummy structure disposed on the boundary isolation structure, wherein the boundary dummy structure has a tapered sidewall that causes a width of the boundary dummy structure to decrease as a distance over the boundary isolation structure increases.

9. An integrated chip structure, comprising:

a source region and a drain region disposed within a substrate, wherein the source region and the drain region have a first doping type and the substrate has a second doping type that is different than the first doping type and that continuously extends between sides of the source region and the drain region;

a select gate disposed vertically over the substrate and laterally between the source region and the drain region; and

a memory device disposed vertically over the substrate and laterally between the select gate and the source region, wherein the memory device comprises a data storage layer arranged between the substrate and a conductive electrode.

10. The integrated chip structure of claim 9 , further comprising:

a boundary isolation structure disposed within the substrate between a memory region of the substrate comprising the memory device and a logic region of the substrate comprising a transistor device.

11. The integrated chip structure of claim 10 , further comprising:

a dummy logic structure disposed over the boundary isolation structure.

12. The integrated chip structure of claim 11 , wherein the dummy logic structure comprises a gate dielectric layer and a dummy logic layer over the gate dielectric layer.

13. The integrated chip structure of claim 11 , further comprising:

a dummy memory structure disposed vertically over the boundary isolation structure and laterally separated from the dummy logic structure by a non-zero distance.

14. The integrated chip structure of claim 13 , wherein the dummy memory structure comprises a lower dummy memory layer and an upper dummy memory layer over the lower dummy memory layer.

15. The integrated chip structure of claim 13 , wherein the boundary isolation structure comprises a sidewall protruding outward from an upper surface of the boundary isolation structure to form a hillock along the upper surface, the dummy memory structure being disposed on the hillock.

16. An integrated chip structure, comprising:

a source region and a drain region disposed within a substrate;

a select gate disposed over the substrate between the source region and the drain region;

a ferroelectric random-access memory (FeRAM) device disposed over the substrate between the select gate and the source region, wherein the FeRAM device comprises a ferroelectric material arranged between the substrate and a conductive electrode; and

wherein the select gate has a bottom surface with a first width and a top surface with a second width that is larger than the first width.

17. The integrated chip structure of claim 16 , further comprising:

a dielectric layer arranged vertically over the substrate and laterally between the select gate and the FeRAM device.

18. The integrated chip structure of claim 17 , further comprising:

a spacer arranged vertically over the dielectric layer and laterally between the select gate and the FeRAM device.

19. The integrated chip structure of claim 17 , wherein the FeRAM device has a bottom surface with a third width and a top surface with a fourth width that is smaller than the third width.

20. The integrated chip structure of claim 17 , wherein the select gate has a curved sidewall facing the FeRAM device.