Method, system and device of serializing and de-serializing the delivery of scan test data through chip I/O to reduce the scan test duration of an integrated circuit
An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.
1. An integrated circuit verification system, the system comprising:
an electronic device under test comprising:
one or more general-purpose input/output (I/O) ports;
a scan serializer including a serializer and a de-serializer, wherein an input of the de-serializer is coupled with the general-purpose I/O ports for serially receiving scan test data and an output of the serializer is coupled with the general-purpose I/O ports for serially outputting test response data; and
one or more circuits under test having a plurality of virtual I/O ports, wherein an output of the de-serializer is coupled with the virtual I/O ports for transmitting de-serialized scan test data to the circuits under test and an input of the serializer is coupled with the plurality of virtual I/O ports for non-serially inputting the test response data from the circuits under test; and
automatic test equipment having a memory and a processor and coupled with the device under test via the one or more general-purpose I/O ports, wherein the automatic test equipment is configured to generate the scan test for testing the device under test, serially transmit the scan test to the device under test via the one or more general-purpose I/O ports, serially receive the serial test response data via the one or more general-purpose I/O ports and analyze the serial test response data by comparing the serial test response data to expected response data stored on the memory.
2. The system of claim 1 , wherein the general-purpose I/O ports do not require the serial scan test data to be formatted according to a packet protocol format.
3. The system of claim 1 , wherein the scan serializer is a digital scan serializer such that the serializer is a digital serializer and the de-serializer is a digital de-serializer.
4. The system of claim 1 , wherein the scan test data as serially transmitted by the automatic test equipment is not formatted into packets.
5. The system of claim 1 , wherein the de-serializer comprises a plurality of shift registers each having a number of registers corresponding to a de-serialization ratio of the de-serializer.
6. The system of claim 5 , wherein the de-serializer inputs the serial scan test data according to a serial clock, holds the serial scan test data static within the shift registers for at least a half cycle of the scan clock, and outputs the de-serialized scan test data according to a scan clock, wherein the scan clock is slower than the serial clock.
7. The system of claim 6 , wherein negative edges of the scan clock and negative edges of the serial clock are aligned.
8. The system of claim 1 , wherein the scan serializer further comprises a bypass component.
9. The system of claim 1 , wherein the virtual I/O ports are inputs to flip-flops of the circuits under test.
10. The system of claim 1 , wherein the expected response data is based on the scan test data.
11. An electronic device under test for operating with automatic test equipment, the electronic device under test comprising:
one or more general-purpose input/output (I/O) ports for receiving scan test data serially transmitted from the automatic test equipment;
a scan serializer including a serializer and a de-serializer, wherein an input of the de-serializer is coupled with the general-purpose I/O ports for serially receiving the scan test data and an output of the serializer is coupled with the general-purpose I/O ports for serially outputting test response data to the automatic test equipment; and
one or more circuits under test having a plurality of virtual I/O ports, wherein an output of the de-serializer is coupled with the virtual I/O ports for transmitting de-serialized scan test data to the circuits under test and an input of the serializer is coupled with the plurality of virtual I/O ports for non-serially inputting the test response data from the circuits under test.
12. The device of claim 11 , wherein the general-purpose I/O ports do not require the serial scan test data to be formatted according to a packet protocol format.
13. The device of claim 11 , wherein the scan serializer is a digital scan serializer such that the serializer is a digital serializer and the de-serializer is a digital de-serializer.
14. The device of claim 11 , wherein the scan test data as serially transmitted by the automatic test equipment is not formatted into packets.
15. The device of claim 11 , wherein the de-serializer comprises a plurality of shift registers each having a number of registers corresponding to a de-serialization ratio of the de-serializer.
16. The device of claim 15 , wherein the de-serializer inputs the serial scan test data according to a serial clock, holds the serial scan test data static within the shift registers for at least a half cycle of the scan clock, and outputs the de-serialized scan test data according to a scan clock, wherein the scan clock is slower than the serial clock.
17. The device of claim 16 , wherein negative edges of the scan clock and negative edges of the serial clock are aligned.
18. The device of claim 11 , wherein the scan serializer further comprises a bypass component.
19. The device of claim 11 , wherein the virtual I/O ports are inputs to flip-flops of the circuits under test.
20. The device of claim 11 , wherein the expected response data is based on the scan test data.
21. A method of operating an integrated circuit verification system, the method comprising:
serially transmitting scan test data with automatic test equipment to one or more general-purpose input/output (I/O) ports of an electronic device under test, the electronic device under test including a scan serializer including a serializer and a de-serializer;
serially inputting the scan test data from the general-purpose I/O ports with the de-serializer, de-serializing the scan test data into de-serialized scan test data, and outputting the de-serialized scan test data to a plurality of virtual I/O ports of one or more circuits under test;
non-serially receiving test response data from the virtual I/O ports of the circuits under test with the serializer, serializing the test response data into serialized test response data, and outputting the serialized test response data to the automatic test equipment via the general-purpose I/O ports; and
serially receiving and analyzing the serialized test response data with the automatic test equipment by comparing the serialized test response data to expected response data.
22. The method of claim 21 , wherein the general-purpose I/O ports do not require the serial scan test data to be formatted according to a packet protocol format.
23. The method of claim 21 , wherein the scan serializer is a digital scan serializer such that the serializer is a digital serializer and the de-serializer is a digital de-serializer.
24. The method of claim 21 , wherein the scan test data as serially transmitted by the automatic test equipment is not formatted into packets.
25. The method of claim 21 , wherein the de-serializer comprises a plurality of shift registers each having a number of registers corresponding to a de-serialization ratio of the de-serializer.
26. The method of claim 25 , wherein the de-serializer serially inputs the scan test data according to a serial clock, further comprising holding the scan test data static within the shift registers for at least a half cycle of the scan clock, and outputting the de-serialized scan test data according to a scan clock, wherein the scan clock is slower than the serial clock.
27. The method of claim 26 , wherein negative edges of the scan clock and negative edges of the serial clock are aligned.
28. The method of claim 21 , wherein the scan serializer further comprises a bypass component.
29. The method of claim 21 , wherein the virtual I/O ports are inputs to flip-flops of the circuits under test.
30. The method of claim 21 , wherein the expected response data is based on the scan test data.