IP Library Granted Patent US 12,243,479
Granted Patent B2
US 12,243,479 · App. 17/869,621 · Granted Mar 4, 2025

Pixel circuit and display panel including the same

Inventors: Jin Woo Jung (Paju-si, KR); Sang Jin Nam (Paju-si, KR); Hyun Suk Lee (Paju-si, KR); Seung Jin Yoo (Paju-si, KR)
Assignee: LG Display Co., Ltd.
G09G3/3233H01L29/7869H01L29/78696G09G2300/0819G09G2300/0842G09G2300/0861G09G2310/08G09G2320/045
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Quick Facts
Patent No.
US 12,243,479
App. No.
17/869,621
Granted
Mar 4, 2025
Kind
B2
Abstract

A pixel circuit and a display panel including the same are disclosed according to embodiments. The pixel circuit according to embodiments includes a first pixel circuit including a first EM transistor to which a pulse of a first EM signal is applied, and a first driving transistor for driving a first light emitting element; and a second pixel circuit including a second EM transistor to which a pulse of a second EM signal is applied, and a second driving transistor for driving a second light emitting element. A node between the first EM transistor and the first driving transistor and a node between the second EM transistor and the second driving transistor are connected.

Claims (34)

1. A pixel circuit comprising:

a first pixel circuit including a first EM transistor to which a pulse of a first EM signal is applied, and a first driving transistor configured to drive a first light emitting element; and

a second pixel circuit including a second EM transistor to which a pulse of a second EM signal is applied, and a second driving transistor configured to drive a second light emitting element,

wherein a node between the first EM transistor and the first driving transistor and a node between the second EM transistor and the second driving transistor are connected,

wherein the first EM transistor is connected between a first power line and the first driving transistor, and responsive to the first EM transistor being turned on, a pixel driving voltage of first power line is supplied to the first driving transistor such that the first driving transistor drives the first light emitting element to emit light,

wherein the second EM transistor is connected between a second power line and the second driving transistor, and responsive to the second EM transistor being turned on, a pixel driving voltage of second power line is supplied to the second driving transistor such that the second driving transistor drives the second light emitting element to emit light, and

wherein the first pixel circuit and the second pixel circuit share a same data line with each other.

2. The pixel circuit of claim 1 , wherein the first pixel circuit and the second pixel circuit share a same scan line with each other, and EM lines of the first pixel circuit and the second pixel circuit are different from each other.

3. The pixel circuit of claim 1 , wherein a light emission duty ratio that the first light emitting element and the second light emitting element emit light during one frame period is greater than a duty ratio of the first EM signal and the second EM signal respectively applied to a gate electrode of the first EM transistor and a gate electrode of the second EM transistor, and

wherein the duty ratio of the first EM signal is a value based on a light emission duty ratio and a number of pixel circuits connected.

4. The pixel circuit of claim 1 , wherein the second pixel circuit includes at least one pixel circuit, and

the first pixel circuit and the at least one pixel circuit receive a pulse of the first EM signal in different frame periods.

5. The pixel circuit of claim 1 , wherein the first pixel circuit further includes:

a first scan transistor connected between a data line and a gate electrode of the first driving transistor;

a first sensing transistor connected between a source electrode of the first driving transistor and a reference voltage line; and

a first capacitor connected between the gate electrode and the source electrode of the first driving transistor.

6. The pixel circuit of claim 1 , wherein the second pixel circuit further includes:

a second scan transistor connected between a data line and a gate electrode of the second driving transistor;

a second sensing transistor connected between a source electrode of the second driving transistor and a reference voltage line; and

a second capacitor connected between the gate electrode and the source electrode of the second driving transistor.

7. A display panel comprising:

a plurality of pixels each including a light emitting element that emits light by a current flowing through a current path formed between a high-potential voltage line and a low-potential voltage line, and

the pixel circuit of claim 1 configured to drive light emitting elements of the plurality of pixels,

wherein the current path is connected between at least two pixel circuits.

8. The display panel of claim 7 , wherein a light emission duty ratio that the light emitting element emits light during one frame period is greater than a duty ratio of the first EM signal applied to a gate electrode of the first EM transistor.

9. The display panel of claim 8 , wherein the duty ratio of the first EM signal is a value based on a light emission duty ratio and a number of pixel circuits connected.

10. The display panel of claim 7 , wherein the at least two pixel circuits receive a pulse of the first EM signal in different frame periods.

11. The display panel of claim 7 , wherein each of the at least two pixel circuits further includes:

a driving transistor supplying a current through the current path;

a scan transistor connected between a data line and a gate electrode of the driving transistor;

a sensing transistor connected between a source electrode of the driving transistor and a reference voltage line; and

a capacitor connected between the gate electrode and the source electrode.

12. The display panel of claim 7 , wherein the at least two pixel circuits share a same scan line with each other, and EM lines of the at least two pixel circuits are different from each other.

13. The display panel of claim 7 , wherein all transistors in a panel including the pixel circuits are implemented with oxide thin film transistors (TFTs) including an n-channel type oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: JUNG, JIN WOO; NAM, SANG JIN; LEE, HYUN SUK; YOO, SEUNG JIN
To: LG DISPLAY CO., LTD.
Reel/Frame 061233/0801 →
Priority Claims (1)
KR 10-2021-0100602 · Jul 30, 2021 · national
Continuity (1)
Related Publication 20230033778A1 · Feb 2, 2023
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Cited By (1)
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