Ferroelectric memory device and method of forming the same

1. A memory cell comprising:

a transistor over a semiconductor substrate, the transistor comprising:

a ferroelectric layer arranged along a sidewall of a word line, the ferroelectric layer comprising a species with valence of 5, valence of 7, or a combination thereof; and

an oxide semiconductor layer electrically coupled to a source line and a bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

2. The memory cell of claim 1 , wherein the species with valence of 5 is nitrogen, and the species with valence of 7 is fluorine.

3. The memory cell of claim 1 , wherein the ferroelectric layer is in contact with the oxide semiconductor layer.

4. The memory cell of claim 1 , wherein a first interface between the ferroelectric layer and the oxide semiconductor layer has a first species concentration higher than a second species concentration of a second interface between the ferroelectric layer and the word line.

5. The memory cell of claim 4 , wherein the ferroelectric layer has a maximum species concentration between the first interface and the second interface.

6. The memory cell of claim 4 , wherein a portion of the oxide semiconductor layer near the first interface has a species concentration.

7. A device comprising:

a semiconductor substrate;

a first memory cell over the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises:

a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being on a sidewall of a first word line, and the ferroelectric layer comprising a species with valence of 5, valence of 7, or a combination thereof; and

a first channel region on a sidewall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a first interface between the first channel region and the first portion of the ferroelectric layer has a species having valence of 5, valence of 7, or a combination thereof, and;

a second memory cell over the first memory cell.

8. The device of claim 7 , wherein a species concentration of the first interface is higher than an oxygen concentration thereof.

9. The device of claim 7 , wherein the ferroelectric layer continuously extends past the first word line and past a second word line that is vertically separated from the first word line by a dielectric layer.

10. The device of claim 7 , further comprising:

a third memory device comprising:

a third portion of the ferroelectric layer being on a second sidewall of the first word line that opposes the sidewall of the first word line; and

a second channel region separated from the second sidewall of the first word line by the third portion of the ferroelectric layer.

11. The device of claim 7 , wherein the species further occupies oxygen vacancies in the ferroelectric layer, the oxide semiconductor layer, or a combination thereof.

12. The device of claim 7 , wherein a ratio of a distribution range of the species to a distribution range of oxygen in the ferroelectric layer is greater than a ratio of a distribution range of the species to a distribution range of oxygen in the oxide semiconductor layer.

13. The device of claim 7 , wherein a ratio of a distribution range of the species to a distribution range of oxygen in the oxide semiconductor layer is greater than a ratio of a distribution range of the species to a distribution range of oxygen in the ferroelectric layer.

14. The device of claim 7 , wherein the second memory cell comprises a second transistor, the second transistor comprising:

a second portion of the ferroelectric layer, the second portion of the ferroelectric layer electrically coupled to a second word line over the first word line, and the second word line and the first word line are separated by a dielectric layer; and

a second channel region.

15. An integrated chip device, comprising:

a plurality of conductive lines disposed over a substrate, wherein the plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines;

a ferroelectric layer extending along sidewalls of the plurality of conductive lines and the dielectric layers;

an oxide semiconductor layer covering a sidewall of the ferroelectric layer, wherein the ferroelectric layer separates the oxide semiconductor layer from the plurality of conductive lines;

a plurality of conductive pillars separated by a dielectric and arranged on a sidewall of the oxide semiconductor layer facing away from the ferroelectric layer; and

a species disposed within the ferroelectric layer and having a valence of 5, valence of 7, or a combination thereof, wherein the species has a concentration that decreases from the conductive pillars towards the conductive lines.

16. The device of claim 15 , wherein the concentration of the species is between about 1E17/cm 3 and 1E20/cm 3 .

17. The device of claim 15 , wherein the ferroelectric layer comprises a first portion in contact with the plurality of conductive lines, a second portion, and a third portion in contact with the oxide semiconductor layer, the second portion and the third portion having a greater concentration of the species than the first portion.

18. The device of claim 17 , wherein a maximum species concentration of the ferroelectric layer is positioned between outermost boundaries of the third portion.

19. The device of claim 17 , wherein the third portion has a species concentration in a first range of about 50% to about 100% of a maximum species concentration of the ferroelectric layer; the second portion has a species concentration in a second range of between about 1% to about 40% of the maximum species concentration, and the first portion has a species concentration that is less than 1% of the maximum species concentration.

20. The device of claim 15 , wherein the species is further disposed within the oxide semiconductor layer.