Polysilicon resistor structures
View Patent ↗The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.
1. A semiconductor structure, comprising:
a semiconductor substrate with spaced apart first and second isolation regions formed therein, wherein the first isolation region is wider than the second isolation region;
a resistor structure disposed on the first isolation region, wherein the resistor structure comprises:
a dielectric layer in contact with the first isolation region;
a nitride layer disposed on the dielectric layer;
a semiconductor layer disposed on the nitride layer, the semiconductor layer comprising a top doped layer overlying a bottom un-doped layer; and
a silicide covering an entire surface of the top doped layer; and
a transistor structure disposed between the first and second isolation regions, wherein the transistor structure comprises:
an interfacial layer in contact with the substrate, wherein the dielectric layer is disposed on the interfacial layer;
a metal gate electrode disposed on the dielectric layer; and
a source/drain region formed in the substrate and adjacent to the metal gate electrode.
2. The semiconductor structure of claim 1 , wherein the silicide further comprises a contact region on the semiconductor layer.
3. The semiconductor structure of claim 2 , wherein the contact region comprises a top contact to direct current flow within the top doped layer along a length of the resistor structure.
4. The semiconductor structure of claim 1 , wherein the semiconductor layer has a thickness between about 10 nm and about 300 nm.
5. The semiconductor structure of claim 1 , wherein the top doped layer of the semiconductor layer has a thickness between about 10 nm and about 300 nm.
6. The semiconductor structure of claim 1 , wherein the dielectric layer comprises a high-k dielectric.
7. The semiconductor structure of claim 1 , wherein the interfacial layer comprises a silicon-based dielectric.
8. The semiconductor structure of claim 1 , further comprising one or more conductive structures on the silicide.
9. A structure, comprising:
a substrate with spaced apart first and second isolation regions;
a polysilicon resistor structure on the first isolation region, comprising:
a metal oxide dielectric layer;
a metal nitride layer; and
a doped polysilicon layer overlying an un-doped polysilicon layer;
a first spacer structure on a first sidewall of the polysilicon resistor structure and along a length of the polysilicon resistor structure in a direction perpendicular to the substrate;
a second spacer on a second sidewall of the polysilicon resistor structure and along a length of the polysilicon resistor structure in a direction perpendicular to the substrate; and
a silicide formed on the doped polysilicon layer and extending from the first spacer structure to the second spacer structure;
a transistor structure formed between the first and second isolation regions, comprising:
the metal oxide dielectric layer;
the metal nitride layer;
a metal gate electrode; and
source/drain regions formed in the substrate and adjacent to the metal gate electrode; and
a top contact to direct current flow within the doped polysilicon layer along a length of the polysilicon resistor structure.
10. The structure of claim 9 , wherein the doped polysilicon layer covers a top surface of the polysilicon resistor structure.
11. The structure of claim 9 , wherein the doped polysilicon layer is uniformly doped.
12. The structure of claim 9 , wherein the doped polysilicon layer is adjacent to the top contact.
13. The structure of claim 9 , further comprising the silicide on the doped polysilicon layer.
14. The structure of claim 9 , further comprising sidewall spacers in contact with the un-doped polysilicon layer.
15. A resistor structure, comprising:
a stacked polysilicon resistor adjacent to a transistor, the stacked polysilicon resistor comprising:
a doped polysilicon layer overlying an un-doped polysilicon layer; and
a top contact to direct current flow within the doped polysilicon layer along a length of the stacked polysilicon resistor;
sidewall spacers in contact with the un-doped polysilicon layer; and
a silicide formed on the doped polysilicon layer, wherein the silicide covers an entire top surface of the doped polysilicon layer.
16. The resistor structure of claim 15 , wherein the silicide covers an entire surface of the doped polysilicon layer.
17. The resistor structure of claim 15 , wherein the silicide comprises one or more of nickel silicide, cobalt silicide, tungsten silicide, and titanium silicide.
18. The resistor structure of claim 15 , wherein the silicide has a thickness in a range of about 50 Å to about 2000 Å.
19. The resistor structure of claim 15 , wherein the doped polysilicon layer has the same dopants as source/drain regions of the transistor.
20. The resistor structure of claim 15 , wherein the transistor is a high-k metal gate (HK/MG) transistor.