3D vertical memory device and manufacturing method thereof
Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.
1 . A three-dimensional (3D) vertical memory device comprising:
a semiconductor substrate;
a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein;
a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and
a gate stack formed on the channel region,
wherein the drain electrode is in contact with a middle portion of the channel region, is spaced apart by a predetermined distance from an upper side of the source electrode, and is in a shape of a line extending in a second direction crossing a first direction.
2 . The 3D vertical memory device of claim 1 , wherein the source electrode is in contact with a lower side of the channel region and in a shape of a line extending in the first direction.
3 . The 3D vertical memory device of claim 1 , wherein the channel region is a vertical columnar shape in which an upper surface, a lower surface, and an inner surface are surrounded by a channel material of a predetermined thickness, and the channel material is a metal oxide.
4 . The 3D vertical memory device of claim 1 , wherein a resistance of the memory device with the channel region having the void therein is expressed as
R
v
o
i
d
=
ρ
h
π
(
r
2
2
-
r
1
2
)
,
where h denotes a height of the channel region, r1 denotes a distance from a center of the channel region to an outer wall, and r2 denotes a distance from the center of the channel region to an inner wall.
5 . A manufacturing method of a three-dimensional (3D) vertical memory device, the method comprising:
forming a source electrode, an insulating film, and a drain electrode on a semiconductor substrate;
etching the drain electrode, the insulating film, and the source electrode to form a trench that defines a region;
depositing a channel material in the trench, wherein the channel material is deposited only on a bottom and an inner wall of the trench to form a vertical columnar channel region having a void structure in the trench; and
forming a gate stack on the channel region,
wherein the drain electrode is in contact with a middle portion of the channel region, is spaced apart by a predetermined distance from an upper side of the source electrode, and is in a shape of a line extending in a second direction crossing a first direction.
6 . The manufacturing method of claim 5 , wherein the source electrode is in contact with a lower side of the channel region and in a shape of a line shape extending in the first direction.
7 . The manufacturing method of claim 5 , wherein the channel material is formed by depositing a metal oxide in a sputtering method, and a void is lastly formed in the trench due to a difference in deposition degree inside and outside the trench.
8 . The manufacturing method of claim 5 , wherein the channel region is a vertical columnar shape surrounded by the channel material of a predetermined thickness provided on an upper surface, a lower surface, and an inner surface.
9 . The manufacturing method of claim 5 , wherein a resistance of the memory device with the channel region having the void structure is expressed as
R
v
o
i
d
=
ρ
h
π
(
r
2
2
-
r
1
2
)
,
where h denotes a height of the channel region, r1 denotes a distance from a center of the channel region to an outer wall, and r2 denotes a distance from the center of the channel region to an inner wall.