Partitioned overlapped copper-bonded interposers
View Patent ↗An interposer, and integrated circuit including an interposer, has a lower surface adapted for bump mounting and an upper surface adapted for copper bonding. An interposer layer includes active interposers and passive interposers. Bridges connect interposers in the interposer layer to produce a functionally large interposer from smaller interposer dies. A core may overlap more than one interposer in the interposer layer. Active interposers are disposed around the edge of the core with passive interposers beneath the core to facilitate heat dissipation.
1 . An integrated circuit comprising:
one or more processing cores;
at least two interposers each of the at least two interposers comprising a first surface adapted for bump mounting and a second surface adapted for hybrid copper bonding; and
an interposer bridge;
wherein:
a processing core of the one or more processing cores is in electronic communication with the second surface of a first interposer and the second surface of a second interposer in the at least two interposers, the interposer bridge in electronic communication with the first interposer and the second interposer.
2 . The integrated circuit of claim 1 , further comprising at least one memory element, the at least one memory element in electronic communication with the first interposer.
3 . The integrated circuit of claim 1 , wherein the first interposer comprises an active interposer and the second interposer comprises a passive interposer.
4 . The integrated circuit of claim 3 , wherein the first interposer and second interposer are disposed beneath the processing core, wherein the processing core is offset from the first interposer and second interposer such that the processing core overlaps the second interposer more than the first interposer.
5 . The integrated circuit of claim 1 , wherein:
each of the one or more processing cores are hybrid copper bonded to each second surface of the at least two interposers; and
each first surface of each of the at least two interposers is bump mounted to a mother interposer.
6 . The integrated circuit of claim 3 , further comprising at least one active component disposed above and in electronic communication with the first interposer.
7 . The integrated circuit of claim 1 , further comprising:
at least one die in electronic communication with the second surface of at least one interposer in the at least two interposers; and
a plurality of vias disposed between the at least one die and a substrate, wherein one or more of the plurality of vias is configured to bypass the at least two interposers and carry signals from the at least one dies to the substrate.
8 . An interposer layer comprising:
at least two interposers, each of the at least two interposers comprising a first surface adapted for bump mounting and a second surface adapted for copper-to-copper bonding, and
an interposer bridge;
wherein:
a first interposer comprises an active interposer and a second interposer comprises a passive interposer, the interposer bridge being in electronic communication with the first interposer and the second interposer.
9 . The interposer layer of claim 8 , further comprising a mother interposer in electronic communication with the at least two interposers via the first surface of the corresponding interposer.
10 . The interposer layer of claim 8 , wherein the second surface of each interposer is adapted for hybrid copper bonding.
11 . A processor comprising:
one or more processing cores;
at least two interposers each of the at least two interposers comprising a first surface adapted for bump mounting and a second surface adapted for hybrid copper bonding; and
an interposer bridge,
wherein:
a processing core of the one or more processing cores is in electronic communication with the second surface of a first interposer and the second surface of a second interposer in the at least two interposers, the interposer bridge being in electronic communication with the first interposer and the second interposer.
12 . The processor of claim 11 , further comprising at least one memory element, the at least one memory element in electronic communication with the first interposer.
13 . The processor of claim 11 , wherein the first interposer comprises an active interposer and the second interposer comprises a passive interposer.
14 . The processor of claim 13 , wherein the first interposer and second interposer are disposed beneath the processing core, wherein the processing core is offset from the first interposer and second interposer such that the processing core overlaps the second interposer more than the first interposer.
15 . The processor of claim 11 , wherein:
each of the one or more processing cores are hybrid copper bonded to each second surface of the at least two interposers; and
each first surface of each of the at least two interposers is bump mounted to a mother interposer.
16 . The integrated circuit of claim 13 , further comprising at least one active component disposed above and in electronic communication with the first interposer.
17 . The processor of claim 11 , further comprising:
at least one die in electronic communication with the second surface of at least one interposer in the at least two interposers; and
a plurality of vias disposed between the at least one die and a substrate, wherein the plurality of vias is configured to bypass the at least two interposers and carry signals from the at least one dies to the substrate.